AVR Freaks

My 0856 AVR instruction set file shows only 1 clock cycle for MUL (unsigned) instruction.

That is a great catch, and simple, really.

The temp register (x) can easily be aside the A register.

That is around 10% increase in performance... :-)

The instruction set shows INC does not affect C Status bit.

The, considering use of movw, and X=r20. A=r21 for example, minimum of 12 cycles for 24 bits positive numbers, for any quantity of right shift bits, being D the reciprocal 2^(8-n).

C0:     MUL C, D           ; 
        MOV C, R1          ; CDH

        MUL A, D           ;
        MOVW A:X, R1,R0    ; ADH:ADL
        
        MUL B, D           ;
        MOV B, X           ; ADL
        ADD C, R0          ; CDH + BDL
        ADC B, R1          ; ADL + BDH + cy
        ADC A, ZERO        ; ADH + cy

Obviously we need to do a total calculation to finish this doubt forever.

The above takes 12 cycles for "n" being any number from 1 to 7.

We can define the question of shifting 3 bytes to the right, in a sequence from 1 to 23 bits.

Lets assume the bytes are A, B and C (lsb), and F will be the counter 1 to 23.

It  is clear that when the count is multiple of 8, just moving the whole byte to the right will be economic, C=B, B=A, A=0, just 3 clock cycles.

This will happens on count of 8 and 16, so we need to keep comparing the count with 8, on each loop of the shifter.

A1:   cpi F, 8
      brlo B0
      mov C, B
      mov B, A
      clr A
      subi F,8
      rjmp A1
      

As we can see above, it is NOT only 3 clock cycles, it takes 11 clock cycles if 16>F>7,  or 19 cycles if F>15 and a waste of 3 if F<8.

The total A0 cycles will be 11+19+21*3 = 93 cycles.

Considering the normal right shift if nothing else;

B0:   ASR A
      ROR B
      ROR C

for each F count, 3 cycles only.

If using only 23 times B0 (not using A0), it would take, it will take a total of 1+2+3...+22+23 shifts = 276 packs of B0, total of 828 cycles.

If mixing A0 and B0, A0 will run on F=8 and 16, and B0 runs 3 times when F<8, it would be;

3 * B0 * (1+2+3+4+5+6+7) = B0*28*3 * 3Cycles = 252 cycles

and we need to add the A0 93 cycles, total of 252+93 = 345 cycles.

Not counting here the loop control and the moving ending values to the use of the application, just bit shifting.

B0 takes care of negative numbers, since the first shift is ASR, it propagates bit 7 down the range.

But A0 has no negative numbers control, it needs to be added.

A1:   cpi F, 8
      brlo B0
      mov C, B
      mov B, A
      clr A
      sbrc B,7   ; if B = 0b1xxxxxx
      com a      ; A=FF
      subi F,8
      rjmp A1

The total A1 cycles will be 13+21+21*3 = 97 cycles.

Total A1 & B0 = 349 cycles, with total control for negative numbers.

A B C exit shifted right  correctly from 1 to 23 times, even if negative.

Now, lets go back to the C0 routine (multiplication) above, it takes 12 cycles per every whole shift, from 1 to 7 shift counts.

It can of course do up to 21 shifts promoting 3 times 7 shifts, fixing the rest with B0 routine.

But as C0 takes 12 cycles, it is the same as B0 running 4 chaining shifts, and 1, 2 and 3 shifts B0 gains.

So, C0 only gains for 5, 6 or 7 shifts.

Also, C0 needs some dressing around, first, the D registers is not F, need a conversion.

F = 7, D = 2

F = 6, D = 4

F = 5, D = 8

This can be done by compare and branch, by table, or other.

and second, it needs the negative number fix and that is not simple.

The negative works by converting all the left zeros bits on resulting A to "1", if the original A7=1, there are several ways to do it.   

I can not see any of the above dressing of C0 be done with less than 10 to 12 instructions, branches, and perhaps more than 15 to 18 cycles.

Lets see, below a very wild brute guessing for dressing B0 with C0, with reciprocal value for D, and dressing for negative numbers.

F is the number of shifts, 1 to 23 in the sequence.

The routine try to use C0 in bumps of no more than 7 shifts, so C1 and C2 below takes care of that and loops to C1 if F>13

C3 do the economical simple 3 instructions low cost shift in case F<5.

C0 is the actual above routine, with the negative dressing, easier than I thought, since temp1 was carrying the value to be ORED to resulting A in case original A was negative.

C1:   tst F
      breq exit
      mov temp,F
      cpi temp,8     ; if count < 8 can go directly for the reciprocal multiplication
      brlo C2
      ldi temp,7     ; if count > 7 then do 7 reciprocal mult and reduce 7 from count

C2:   sub F,temp
      cpi temp,5     ; if count < 5 no reciprocal for this, just bare B0 times count
      brlo C3        ; this line and the above could be eliminated with expense or more cycles below if temp<5

      ldi D,2     
      ldi temp1, $FE ; dressing left 7 bits if negative  
      cpi temp,7     ; if count =7 D=2 and do reciprocal
      beq C0

      ldi D,4
      ldi temp1, $FC ; dressing left 6 bits if negative
      cpi temp,6     ; if count =6 D=4 and reciprocal
      breq C0

      ldi D,8
      ldi temp1, $F8 ; dressing left 5 bits if negative
      cpi temp,5     ; if count =5 D=8 and reciprocal
      breq C0

C3:   asr A          ; here repeat bare shift "temp" times, up to 4, economical.
      ror B 
      ror C 
      dec temp      
      brne C
      rjmp C1

C0:   sbrs A,7       ; skip next if original A is not negative, bit 7=0
      clr temp1      ; no negative bits
      ;  here the regular C0, reciprocal multiplication, A B C and D are set
      or A,temp1     ; repopulate left bits if original A was negative

We have a bunch of instructions to accommodate B0 and C0 routines to run together.

Considering we will have at least 4x B0s when F is lower than 5, one extra B0 when F=21, C0 when F=5, 6, 7, 12, 13, 14, 18, 19, 20.  

We have around 20 cycles per iteration just for the overhead/dressing, guessing 1/2 of it per F value, 200 cycles, plus the 349 cycles above, 549 cycles for B0 & C0, still better than 828 for just B0 chain sequence.  Need to simulate the above to get the real cycles count, and perhaps optimize the brute code.  May be including the A1 code (97 cycles) could reduce 2xC0 (8 and 16).

But A1 & B0 do it all with only 349 cycles, so that is the winner, forget the reciprocal multiplication, even being a good idea, the overhead murdered it bloody violently.

And for the curious, yeah, I had nothing better to do this Saturday evening.  ;-)  ... and that closed the doubt.

What I would love is to have a second set of registers, R00' to R31' that you could load with a specific value, and activate a compare R05 with R05' (for example) and set a flag or an interrupt...

Think, you are plotting pixels on a color LCD, the screen is like a scope, there are X and Y axis lines in the center of screen, your line being plotted will cross the axis, but you don't want to destroy (plot over) the axis.

So, for every pixel you put on LCD, you need to compare if the address is the same of the axis, and if yes, ignore that plot.

For that simple verification you added 4 or more instructions FOR EVERY pixel plotted, comparing addresses.

If you could compare in hardware the registers containing the address to plot, against a preset value in the counterpart registers, and be interrupted ONLY when it matches... wonderful, isn't it? 

May be more simple, R24&R25 and R26&R27 could be compared against any other register pair, programmed in two other compare register I/Os, CPRA and CPRB (8 bits each)

CPRA is the address of the low register (R00~R31, 0x00~0x1F) to compare against R24&R25 and CPRB the same to R26&R27.

Bit 7 of CPRA or CPRB if "1" enables interrupt, Bit 6 is a flag that will be "1" whenever CPRA or B matches the register vectored.

CPRA = 0x06 means R06 will be compared against R24, and R07 against R25, when matches, CPRA bit 6 will be up.

CPRA = 0x86 means the same, but interrupt (vector CPRA_INT) will be generated.

Hardware compare for registers, the same as used for counter/timers.