I have a HW that uses I2S bus, in 32b, Stereo mode,
i.e. data on output pin I2S/SD are organized: 32b_L, 32b_R, 32b_L, 32b_R,...
My application uses only the L channel, R is not audible, so the routine that fills audio data into buffer (pointed by DMA descriptor) organizes data this way:
32b_sample[i], 0, 32b_sample[i+1], 0, 32b_sample[i+2], 0, 32b_sample[i+3], 0,... i.e. every second sample is 0 (all sample to R channel).
It is not optimal usage of the buffers, as 50% is wasted for useless zero-samples.
According to datasheet 29.9.7 Serializer n Control, there is bit SERCTRL.DMA,
if DMA=1, then even- and odd-numbered slots use separate DMA channels.
And this is what I don't understand.
I currently have solution with I2S->SERCTRL.DMA=0 (i.e. single DMA channel used for even- and odd-numbered slots) and it works ok.
As a trigger is selected DMAC->CHCTRLB.reg = 0x00802B00;
// TRIGSRC[5:0]=0x2B .. I2S TX 0 Trigger
Q1) is it correct to expect that setting I2S->SERCTRL.DMA=1 would cause, that for example DMA Channel 0 could be used for L samples only, and Channel 1 for R samples only ?
Q2) if yes, which trigger must be selected for DMA and for DMA ? Should both be 0x2B (I2S TX 0 Trigger) ?
I don't understand how is then determined, which of the 2 DMA channels us used for L and for R channel.
I tried to set I2S->SERCTRL.DMA=1, use DMA Channels  and , both configured with trigger=0x2B,
descriptors of both DMA Channels have DSTADDR=I2S->DATA.reg,
but it doesn't work.
Is there anybody with experience with I2S->SERCTRL.DMA=1 ?