(I'm targeting an ATtiny214 but the TWI slave section of the Rev C datasheet seems common to other 1-Series. There are no applicable TWI errata for that revision.)
Can't help thinking there's something I've misunderstood; I'm puzzled by the slave state-machine diagram (Figure 26-16). Suppose a slave gets SLA+R and won't be able to process the read: it should NACK to inform the master. The master then has two options:
- It can retain ownership of the bus and issue a Repeat-Start, then either retry the slave or address a different one. (That possibility's shown in the diagram, albeit oddly: the NACK transition via S1 returns to a Start but in this context, without an intervening Stop, strictly it should be a Repeat-Start.)
- Instead the master can give up, issuing a Stop to complete the transaction and relinquish the bus.
Is there something I've missed which explains why that second option isn't shown in the diagram? It's available if the slave gets SLA+W and won't be able to process it, so why not for SLA+R?
From the diagram it appears a read transaction can't be completed with Stop except via an ACK from the slave followed by a data interrupt. That seems a strange exit path if the slave can't process the read.
Do we just have to live with it: ACK and proceed to the data interrupt, then issue a completion without returning data which we've told the master to expect? And if so, where's the NACK to prompt the master to quit with Stop, instead of assuming it might be worth retrying endlessly while hogging the bus?