Atmel Start: Clockgenerators have 0Hz with GCLK_IOx

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DrDatasalad
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Posted by DrDatasalad: Thu. Jan 14, 2021 - 02:13 PM
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Hello,

I am using Atmel Studio 7 and want to setup a new Project with Atmel Start,
for SAME54 Xplain board. Now I've experienced bugs in Atmel Start:

- when configuring the source of any clock generator to be "Generic clock generator input pad",
the output frequency is always 0Hz - despite having defined "external pad frequency" to 4000000.

Is this a known "feature"?

- when trying to set an external 4MHz as input to an XOSC it states 8MHz minimum.
Although having not activated "Crystal connected". This limt is true for a crystal, but should not apply for an external frequency input.
In data sheet I found no minimum limit for that...
Thanks for help.

This topic has a solution.

Surprise: As soon as one's doing it correctly - it works!

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Tools, Atmel Software Framework (ASF) and Atmel Start (ASFv4) (ARM-related), solved
Last Edited: Fri. Jan 29, 2021 - 06:57 AM
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Bruce_s
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Posted by Bruce_s: Fri. Jan 29, 2021 - 05:28 AM
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Hi,

On the Generic clock generator block setting, there is a box for the division factor. You can use 8MHz input and set the division factor to 2 so the output will be 4MHz for the lower frequencies you can use 32KHz as a reference.

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DrDatasalad
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Posted by DrDatasalad: Fri. Jan 29, 2021 - 06:53 AM
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Hi Bruce_s,

yes I could do so, but then there is the division factor set to 2 and when I am using my real 4MHz clock it gets devided, which is not what I want.
Meanwhile I found out that I can leave 8MHz to XOSC setting and division factor 1. So the PLL frequency is calculated to 240MHz that I directly use as CPU clock. Surprisingly it doesn't prohibit to generate the project with such a setting. cheeky Overclockers are welcome?

I did extensive tests for the FDPLL200M. The maximum reference frequency is stated as 3,2MHz in the data sheet. But I got the PLL lock on up to 6MHz!
And that without more jitter than with lesser frequencies. The jitter under all conditions looks awful even when divided down to 4MHz.
And all the filter settings doesn't provide any improvement.
Microchip support stated that there is probably no lower frequency limit to XOSC when supplied with external clock.
Despite that, with 4MHz XOSC the PLL is not able to signal a lock. One must activate the bypass and wake up fast (mentioned in errata sheet).
Otherwise the init function hangs up. Astonishingly with bypass, the PLL signals a lock afterwards! One can only wonder, but couldn't understand...
I don't have the hope that this bug will be corrected soon.
So to me, my problem is solved somehow.

Surprise: As soon as one's doing it correctly - it works!

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