Interrupt Question

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Here's a scenario:

Timer 0 Overflow interrupt is enabled
Global interrupts are enabled

Later on, the code does a CLI.
Timer 0 Overflows.

When the code SEIs, does the Timer 0 interrupt then happen, or is it skipped?

Thanks for the insight!

Kurt

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If you read the datasheet carefully, you'll find the interrupt flag for the timer is latched. When the interrupt is serviced, the hardware will reset this flag or you can reset it yourself.

so, when the SEI() is executed and the timer0 interrupt is pending, it will be serviced assuming there is no other higher priority interrupts pending.

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I missed that, thanks! Do you recall if it's the same with other interrupt types?

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All interrupts require 3 conditions to be met before the irq routine executes- 1) global irq flag is set, 2) irq enable bit is set for the irq routine, 3) irq flag is set (or a bit in a register is cleared, for the few that do not use 'flags').

The irq flag set by hardware remains set until the irq routine is run (which clears the flag for you), OR you clear it yourself (usually by writing a 1 to the flag bit).

If you ran timer0 (lets assume timer0 irq enable is off), and it overflowed at any time, the timer0 overflow flag will be set and remain set. Which means if you later turned on the irq enable bit for timer0 and enable global irq's, you will get the timer0 irq interrupt right away.

Some irq's like SPM irq and EEprom irq do not have a 'flag', but will interrupt when the SPM or EEprom is done writing, and will 'continue' to interrupt when no writing is taking place, so in those cases you have to clear the irq enable inside the irq (other bits are used as the 'flag', but there is no 'clearing' of the 'flag').

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Thanks guys!