I've just read the section about the EERIE (EEPROM Ready Interrupt Enabled) bit in the datasheet of ATmega328P. It says,
"Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to
zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is
cleared. The interrupt will not be generated during EEPROM write or SPM."
So does this mean that, if you have set EERIE to 'one', an interrupt request will occur while EEPE is cleared (even after serving the ERDY interrupt) or does this only happen once when the EEPE bit flips from 'one' to 'zero' ?
I think it is the former, but I am not 100% sure. I've tried to test this case in a simulator under Linux, but it seems that no interrupt occurs at all.
Thanks for reading.