Hello everyone,
I am working with the rotary pulse generator to create pulse that increases when turned clockwise and decreases other way, but I can't figure out the issue with my code. I tried various way but it doesn't work. lf anyone can let me know the issue that would be really helpful
.include "m328pdef.inc" .cseg // configure port pins cbi DDRD, 2 // signal A - connected to RPG cbi DDRD, 3 // signal B - connected to RPG sbi DDRD, 4 // LED output - connected to LED to GND // Tracks current & previous state of RPG .def current_state = r16 .def previous_state = r17 // Duty cycle range .equ upper_cycle_limit = 200 .equ lower_cycle_limit = 30 .equ half_duty_cycle = 115 .def duty_reg = r18 ldi duty_reg, half_duty_cycle // Rotational speed .def rate_reg = r19 ldi rate_reg, 0x02 // Timer registers .def tmp1 = r23 .def tmp2 = r24 .def count = r25 ldi r30, 0x02 out TCCR0B, r30 ldi r30, 0x00 // RPG signal identification .equ both_on = 0x00 .equ a_on = 0x01 .equ b_on = 0x02 .equ both_off = 0x03 // Main loop main: nop nop rcall read_RPG nop rcall which_direction nop cbi PORTD, 4 ldi count, 220 sub count, duty_reg rcall delay sbi PORTD, 4 mov count, duty_reg rcall delay rjmp main // Read RPG Input read_RPG: nop push r28 push r29 ldi r28, 0x01 ldi r29, 0x02 mov previous_state, current_state ldi current_state, 0x00 sbis PIND, 2 add current_state, r29 sbis PIND, 3 add current_state, r28 pop r29 pop r28 ret // Which way is RPG is being turned which_direction: nop cpi previous_state, both_on breq which_end cpi current_state, both_off breq current_low rjmp which_end current_low: cpi previous_state, a_on breq counter_clockwise cpi previous_state, b_on breq clockwise rjmp which_end which_end: ret // counter-clockwise turning counter_clockwise: sub duty_reg, rate_reg cpi duty_reg, lower_cycle_limit brsh end_ccwise ldi duty_reg, lower_cycle_limit end_ccwise: ret // clockwise turning clockwise: add duty_reg, rate_reg cpi duty_reg, upper_cycle_limit brsh recover_upper rjmp end_cwise recover_upper: ldi duty_reg, upper_cycle_limit end_cwise: ret delay: in tmp1, TCCR0B ldi tmp2, 0x00 out TCCR0B, tmp2 in tmp2, TIFR0 sbr tmp2, 1<<TOV0 out TIFR0, tmp2 out TCNT0, count out TCCR0B, tmp1 wait: in tmp2, TIFR0 sbrs tmp2, TOV0 rjmp wait ret