FPGA, here I come!

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buserror
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Posted by buserror: Thu. Oct 4, 2007 - 12:30 AM
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Pfew. after quite a lot of work, I now have a workflow to program a fpga board!
Got a cheapo ($75) XC3S200 board from ebay, installed the Xilinx ISE under linux (debian), got a USB JTAG adapter (amontec JTAGKey) and configured the whole lot to allow programming the board from the IDE.

And guess what, I got a blinking LED ! Huzzah ! :D

The thing to note is that fpga compilation is /slow/. My blinky led take about 3 or 4 minutes grinding and compiling to get the binary file; and thats just about a page of VHDL !
The PC is not horribly slow (P4 2Ghz/1GB RAM) but it's very, very sluggish in the IDE.

But it works, that wasn't trivial too :D

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jayjay1974
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Posted by jayjay1974: Thu. Oct 4, 2007 - 10:22 AM
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Yes, the whole compilation process is very slow. It can easily take days for complex designs. It's a very complex process. Especially when you're running out of routing resources compilation time goes up dramatically. Basically every time it lays out a PCB with automatic placement and routing of all components :D

I don't think a few pages of VHDL will increase the time much, most time is likely overhead of loading all the different executables.

I have never used Xilinx ISE, I use Altera stuff :)

FPGAs and VHDL are fun. Especially that everything happens at the same time takes a little getting used to, sequences have to be coded explicitly.

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daqq
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Posted by daqq: Thu. Oct 4, 2007 - 11:13 AM
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Have fun! I'll have to learn some day to play with them :-D

There are pointy haired bald people.
Time flies when you have a bad prescaler selected.

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buserror
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Posted by buserror: Thu. Oct 4, 2007 - 01:10 PM
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Yeah the 'parallel' programming looks like fun. mind boggling too, I actualy /dreamt/ of vhdl last night, I need medical help :D

Realizing that the code doens't 'run' is great too; it's just 'there'!

There are even implementation of the AVR core /into/ the FPGA - I will have to play with that, it sounds awesome :-)

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leon_heller
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Posted by leon_heller: Thu. Oct 4, 2007 - 06:20 PM
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I've got one of the Xilinx/Digilent S3 boards (they start at $99). They are very popular so there are lots of applications that can be downloaded for it which work straight off.

Leon

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Bronze MarkJohanEkdahl
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Posted by JohanEkdahl: Thu. Oct 4, 2007 - 06:57 PM
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Hey buserror! Any chance that you might share the blibking LED project? I am slowly, too slowly, moving towards playing with FPGAs (also), and any small example will help me.

I wont be visiting 'freaks for a couple of days, but a PM answer to this question would be great!

Thanks to a generous fellow 'freak I have a Diligent Xilinx board om my desk (and I'll get around to getting a Spartan-3E Starter Kit any year now...). I'd love to try that out with yor blinky!

At my present work there are three FPGA/VHDL coders that stuff a large FPGA full (often more than full...) with high speed signal processing code. They have their own dedicated Linux system, with more memory than you can imagine, and running at warp 9.2 or so. They still think its slow...

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here. 

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buserror
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Posted by buserror: Thu. Oct 4, 2007 - 09:38 PM
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Well, it's my first bit of vhdl so it's embarassing :D

It blinks a led every 1/2s (my default crystal is 25mhz) and it applies a 10% PWM on it.
It's not much, but it works :D
I should probably declare 'y' as a 'signal' and hook the pwm on that instead...

----------------------------------------------------------------------------
---	A half second blink-a-led module
---   This verifies that clk, btn and led all works properly. 
---	Hold btn to turn off the led.
---	The frequency of clk is 25MHZ.
---	The btn input is active low and requires a pull-up to work properly
----------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity blinkaled is
    Port ( clk : in std_logic;
           btn : in std_logic;
           led : out std_logic);

	attribute PULLUP : string;
	attribute PULLUP of btn : signal is "TRUE";

end blinkaled;

architecture Behavioral of blinkaled is
begin

process(clk, btn)
variable x : integer;
variable p : integer;
variable y : std_logic;
begin
	if btn='0' then
		y:='0';
		x:=0;
	elsif clk'event and clk='1' then
		if x = (25000000 / 2)	then
			y:=not y;
			x:=0;
			p:=0;
			led <= y;
		else
			x := x + 1;
		end if;
		if y = '1' then
			p := p + 1;
			if p = 1 then
			   led <= '0';
			elsif p = 10 then
				led <= '1';
				p := 0;
			end if;
		end if;
	end if;
-- led<=y;
end process;


end Behavioral;

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buserror
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Posted by buserror: Tue. Oct 9, 2007 - 12:14 AM
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A bit more play with Xilinx's IDE! This time a "Knight Rider" style led ramp, using two complementary PWM phases for consecutive states.
I played here with the state machine constructs, 'sized' integers to make sure not to waste register bits.
The main work was to explore the "floorplaner", the simulator (cooooooooool!) and generating 'rom' files to upload into the config flash. Oh and having a 'toplevel' VHDL components to instantiate the different modules.
Also figured out how to use the clock manager components to get 50Mhz out of the 25Mhz crystal.

A fantastic amount of stuff yet to be learned! I'm making a simple SPI interface for now. I'll try i2c after that.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ledramp is
    Port (
			clk : in std_logic;

			ramp: out std_logic_vector(7 downto 0));

end ledramp;

architecture Behavioral of ledramp is
	type state_type is (PULSE, SHIFT);
	signal state : state_type := PULSE;
	
	type pwm_range is range 0 to 3000;
	constant pwm_max : pwm_range := 3000;
	
begin
	
	process (clk)
	variable up : std_logic_vector(7 downto 0) := "00000001";
	variable down : std_logic_vector(7 downto 0) := "00000000";
	variable direction : std_logic := '0';
	variable mark,phase : pwm_range := 0;
	begin
		if rising_edge(clk) then
			case state is
				when PULSE =>
					if phase = 0 and mark > 0 then
						ramp <= up;
					end if;
					if phase = mark then
						ramp <= down;
					end if;
					phase := phase + 1;
					if phase = pwm_max then
						phase := 0;
						mark := mark + 1;
						if mark = pwm_max then
							state <= SHIFT;
							mark := 0;
						end if;
					end if;
				when SHIFT => 
					down := up;
					if direction = '0' then
						if up = "10000000" then
							direction := '1';
							up := "01000000";
						else
							up := up(6 downto 0) & up(7);
						end if;
					else
						if up = "00000001" then
							direction := '0';
							up := "00000010";
						else
							up := up(0) & up(7 downto 1);
						end if;				
					end if;
					state <= PULSE;
			end case;
		end if;
	end process;
	
end Behavioral;

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jayjay1974
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Posted by jayjay1974: Tue. Oct 9, 2007 - 12:32 AM
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Make your own processor, that's fun :)

What's also great fun is to design a complete system on a chip with a microprocessor and peripherals. I use Altera NIOS II/SOPC builder, it's nice to select a processor from the list, and add what you need like SPI, UART etc. Need another UART? Just add it :) Need a SD card interface that reads sectors right into memory without processor overhead? Write some VHDL code to just do that :) Want a TFT controller? Just write it 8) Need to decode JPGs faster? Add a fully parallel IDCT core as a custom instruction 8)

Great stuff, unfortunately only suitable for the more bigger systems because you need external RAM, flash storage, configuration device, usually multiple voltage regulators etc.

Inputs aren't outside world friendly (no schmitt trigger inputs like on an AVR; usually not 5V tolerant, usually risetime requirements).

Though there are exceptions of course.

Simulation is really needed when your designs grow bigger. You can't sprinkle printf()'s everywhere or set a breakpoint ;) Though (at least Altera offers this) you can install an onchip logic analyser and read the captured data out via JTAG, in near realtime.

But it's great fun, you're a chip designer now :D

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buserror
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Posted by buserror: Wed. Oct 10, 2007 - 12:09 AM
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I've been toying with 'ghdl' and 'gtkwave' which is some sort of simulator, free. I haven't got very far, since my very simple example up there doesn't doesn't generate the signal I would expect... but the tools exists, and are quite a bit faster than Xilink's !
If I get it to work properly (I emailed the author) it might be a very good development platform for doing the 'bulk' programming in vhdl...

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jgmdesign
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Posted by jgmdesign: Wed. Oct 10, 2007 - 12:03 PM
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Buserror:
I have been using CPLD's for years and can relate with your satisfactions! What I like about using them is that you eliminate so much pcb space for discretes, reduce the worry about traces radiating, they run way faster, and reworking the code is easier than relaying out a board. I don't do much with FPGA's as they are a little scary to me, but this thread of yours has sparked my interest in taking another crack at them....keep posting

Jim

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buserror
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Posted by buserror: Wed. Oct 10, 2007 - 02:00 PM
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I shall ! :-) The really powerful thing seems to be able to integrate as many 'cores' as you like, and even complete, reconfigurable microprocessors. Nowhere near as energy efficient as an AVR of course, but for some tasks it seems really, really cool.

There are no 'communities' for fpga users, it's a bit too bad. So, I'm scavenging information of the internet and trying bits and pieces.

I found this Shock and awe VHDL tutorial to be quite useful. Not too much useless information.

What CPLD do you use ? Xilinx has an offer for a Coolrunner II starter kit for $25 at the moment; unfortunately, none of the 'distributors' have a web-front and none are in the UK :/

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Geoff
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Posted by Geoff: Thu. Oct 11, 2007 - 02:47 AM
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ahh i remember doing them at uni - cool fun, I can only imagine how awesome (but daunting) it would be to design something in a larger scale. having it run fully in hardware would be impressive :D

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jgmdesign
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Posted by jgmdesign: Thu. Oct 11, 2007 - 11:45 AM
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Buserror:
I use Lattice and Atmel. The coolrunners were originally from Phillips, but when they were sold to xilinx I stopped using them because my local xilinx fae is an ass and pissed me off once. I may have to re-look at xilinx as they do have some cool stuff, and the fae died so maybe a fresh start is in order

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

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letcat
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Posted by letcat: Thu. Oct 11, 2007 - 12:31 PM
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Hi all,
just thought I'd throw in my 2 cents on the FPGA subject. If you're new to the VHDL/FPGA world (or even an oldschool VHDL wizard for that matter), you could benefit from browsing through the VHDL design metodology developed by Mr Gaisler, the designer behind the LEON open-source SPARC CPU gaisler.com. You could have a look at a brief description of the metodology here http://www.gaisler.com/doc/vhdl2proc.pdf.

The LEON2/3 processors/SoC are all implemented using this method, the sources are a very good place to learn structured VHDL design from - regardless if you're developing your first 100-gate LED flasher or a milion-gate multimedia SoC or satelite control system.

Gaisler.com (no, not affiliated :) ) also provides some Xilinx FPGA boards, including a "low cost" Spartan3-1500 board with some VGA/USB/Ethernet/PS-2 connectivity - truly great fun to play with!

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buserror
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Posted by buserror: Thu. Oct 11, 2007 - 04:17 PM
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thanks letcat; the .pdf is good reading; however I wonder if the method described generate 'heavier' implementation than the more the concurent approach. Maybe it's a question of 'making it work' and maybe make a more optimized version afterward ? I'm certainly going to play with it, just the suggestion of using 'record' types looks like a very nice improvement.

Thanks for the 'low cost' board, 750 euros is about 10 times more than what I spent so far ! :-)
I think my next module will be this one -- it's very cheap, has more IO and a lot more RAM/Flash. Generaly more tinker friendly!
After that I hope I'll be confident enough to make myself a board, most probably with one of the AV32UT3A0512 samples I have a a X3S400. With the bus interface shared directly into the fpga, it could be a hugely powerful combo...

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buserror
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Posted by buserror: Thu. Oct 11, 2007 - 05:02 PM
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BTW, I had another go at ghdl/gtkwave, and in fact, they work just fine ! It was just me who was trying to look at 100 clock cycles when my module was downclocking /3000th of the clock I was feeding it with the tester module :-)

doh !

I'm back on track then, the ghdl /seems/ to be nice, and you can really write & test stuff a lot faster than in the ISE.

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Bronze MarkJohanEkdahl
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Posted by JohanEkdahl: Thu. Oct 11, 2007 - 07:21 PM
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Buserror!
That looks like one fine tutorial! Excellent find! Thank you for sharing!

Quote:

I think my next module will be this one [link to the Propox MMfpga12] -- it's very cheap, has more IO and a lot more RAM/Flash. Generaly more tinker friendly!

Please note that if you plan to buy both the FPGA module, the evaluation board and the programming cable the price is $132. If you add $17 you have $149 which will buy you the Spartan-3E Starter Kit which has
- A bigger Spartan-3E (XC3S500 instead of ..200)
- A CoolRunner-II CPLD
- 128 Mbit Parallel Flash, 16 Mbit SPI Flash, 64 MByte DDR SDRAM
- 16x2 display and 8 LEDs
- 4 switches, 4 pushbuttons, one rotary encoder
- Ethernet, PS2 keyboard port, VGA (low on colors, but still...)
...and the list goes on (eg. D/A and A/D converters)...
I have had one home on loan, and it sure impressed me although I didn't have the time to play around a lot. Only drawback I have seen is the breakout abilities. Some 20 or so signals on ordinary "jumper pins". If you want more you'll have to get a 100-pin hirose connector.

The board (and hirose connectors) is available in europe from Trenz Electronic in Germany (at a somewhat higher price). In the US I'd have a look at eg. Digikey.

Xilinx web-page on this board: http://www.xilinx.com/xlnx/xebiz...

Trenz Electronics web-page on this board: http://shop.trenz-electronic.de/...

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here. 

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

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letcat
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Posted by letcat: Thu. Oct 11, 2007 - 07:27 PM
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buserror:

Quote:
however I wonder if the method described generate 'heavier' implementation than the more the concurent approach.

Yeah I can actually relate to your concern, that's the same way I felt the first time we got introduced to this high abstraction-level concept. It's a bit like the assembly vs. C debate... Generally it's been at least my feeling that the synthesizis tools are actually very good at implementing efficient logic, even from high-level behavioral descriptions. Of course it may be possible to write 'bad code' that the tools can't interpret and synthesize efficiently, while the traditional structural data-path method with lots of simpler low-level components like adders/flipflops/counters etc typically leaves more hints for the tools and less risk to 'misinterpret' what you want to do.

Just like it's possible to beat optimizing c-compilers with hand-optimized asm, it's surely possible to hand optimize logic both at the HDL level and using extensive constrains to manually place-and-route it to really efficiently utilize a certain FPGA architechture etc. But again citing the LEON2 CPU as example, the entire 32-bit SPARC SoC is synthesized to about 30k gates when targeting a 0.25u std-cell CMOS process, that's certainly not unexpectedly inefficient.

The Propox module indeed looks very cool, and cheap enough to get one just for fun!

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letcat
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Posted by letcat: Thu. Oct 11, 2007 - 07:45 PM
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Hey, I hope I'm not getting too far off-topic but one advice for all aspireing VHDL-developers out there is: use x/Emacs for all your VHDL-editing pleasure! The emacs, together with 'vhdl-mode' http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html is IMHO an unbeatable combination when it comes to editing, despite a keyboard "short-cut" learning curve equal to Mt Everest. The editor is actually writing so much of the code for you that if you ever have to write something in another editor, you'll find that you're in fact not really sure of the language syntax and constructs :)

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indianajones11
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Posted by indianajones11: Mon. Oct 15, 2007 - 09:05 PM
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buserror, you wrote that there aren't any fpga communities. Try fpga4fun.

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buserror
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Posted by buserror: Tue. Oct 16, 2007 - 10:58 AM
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Thanks IJ, I'll have a look.

I've been letting all the data I digested 'settle' a bit, I wrote several versions of an i2c master to see what sort of method I felt comfortable with. It's quite fun. I'm getting my head around 'pipelining' and buffering too.
I'm using the 'record' method described in the pdf mentioned on the previous page, it certainly does save a lot of cut/paste and makes the code more 'consistent' somehow.

ghdl / gtkwave is the way to go BTW, it's one of the rare compiler front-end that gives you meaningful error messages. And gtkwave is a bit quirky, but it does the job...

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buserror
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Posted by buserror: Tue. Oct 16, 2007 - 12:59 PM
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Droooooooooooooooooollll

Look at that board

Problem is 1) I'm not a student 2) you can't use the free WebPack.

Already thinking about ways to go around these little problems :-)

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jayjay1974
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Posted by jayjay1974: Tue. Oct 16, 2007 - 01:09 PM
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At work we have this board (see attachment). It's a Avnet Spartan 3 evaluation board. I think we have never used it and maybe my boss might sell it if I ask.

Attachment(s): 

Image icon avnet_spartan_3_board (Medium).jpg
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buserror
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Posted by buserror: Tue. Oct 16, 2007 - 01:52 PM
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Sure, it looks nice; what model is it ? Message me if you decide to get rid of it :-)

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goujam
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Posted by goujam: Tue. Oct 16, 2007 - 02:42 PM
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Oh the memories of uni. I loved VHDL on FPGA's of course we had to make a trafic light controller. Running it on a FPGA was the most fun way of doing it. Wish I had gone more into it and got a job using them. Micro's will have to do for now

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jayjay1974
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Posted by jayjay1974: Tue. Oct 16, 2007 - 02:48 PM
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ADS-XLX-SP3-EVL400

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daqq
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Posted by daqq: Tue. Oct 16, 2007 - 04:54 PM
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Quote:
Droooooooooooooooooollll
Look at that board
Problem is 1) I'm not a student 2) you can't use the free WebPack.
Already thinking about ways to go around these little problems

Yipes! Amazing system, but I can't imagine what I'd use it for. :-D

There are pointy haired bald people.
Time flies when you have a bad prescaler selected.

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buserror
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Posted by buserror: Tue. Oct 16, 2007 - 07:49 PM
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daqq, just imagine plugging the sata port to your workstation and use the whole board as a 'virtual hard drive' coprocessor with 300GB/s bandwidth...
Write a file to the disk, read it again and it's been processed. Or map a 'drive' region on the workstation and get a huge shared address space with the 2 PowerPC, and such.

I can see lots of possibilities from here :D :D

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outer_space
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Posted by outer_space: Tue. Oct 16, 2007 - 11:14 PM
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Very interesting topic adding a fpga to a desktop system for extra power. There are Spartan PCI-E parts available now. I wonder how fast dvd or music ripping could be completed?

As far as the lengthy time it takes to compile big designs, maybe xilinx themselves could use this idea buserror mentions to speed up compilation. Fast autorouting anyone??

The main issue with having a FPGA coprocessor is that with the wrong program you can break the fpga.

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jayjay1974
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Posted by jayjay1974: Tue. Oct 16, 2007 - 11:25 PM
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I heard from a FAE that synthesis and fitting don't lend themselves very well for parallelization. So just adding more processors all compiling stuff in parallel seems impossible or doesn't improve things well enough to be worthwhile, so they abandoned the idea.

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buserror
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Posted by buserror: Wed. Oct 17, 2007 - 12:08 AM
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Well stuff like (pcb) autorouting certaintly could; it's the typical task where you 'weight' options and toss the one that behave badly. Scatter Gather!

For synthesis it's a different ball game. To compile normal scalar stuff you can make a huge tree of dependencies, sort it and dispatch 'branches' on several threads before the link, but I have no idea how the FPGA tool work.
However I'm sure stuff /could/ be faster, I just can't explain the time it takes to generate one little tiny binary file. And it's not really just the processing that is slow, it's /everything/ that is slow, from text editing to searching to just clicking on items. Java Alert ! :D

@outer_spave: Hmmm PCI-E options ? Without having to pay for the "IP Core" ? :D

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jayjay1974
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Posted by jayjay1974: Wed. Oct 17, 2007 - 12:20 AM
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The PCI-E support is likely only the I/O standard that's supported. Maybe they included the SERDES too. Likely the higher level stuff is not free. But you could write your own of course :)

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letcat
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Posted by letcat: Wed. Oct 17, 2007 - 01:15 PM
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If you want some serious FPGA power, check out these bad boys:
http://www.synplicity.com/products/haps/hardi_welcome.html
Just pile up a cluster of 10 or so HAPS-54... 8)

Anyway, the concept of adding FPGA computing power to a standard workstation is indeed interesting. And it gets seriously cool when taking runtime reconfiguration into account (google "reconfigurable hardware"). In principle a FPGA is configured with a permanent part for e.g. a small "interface framework", while the major part of the chip is dynamic, that can be run-time (re-)configured by downloading "partial bit-files" on the fly...

Imaginge watching a HD movie, then the system just instansiates a harware H.264 decoder that does all the crunshing, maybe even optimising the decoder algorithms HW in runtime to tune its efficiency to the particular videostream characteristics. Then you fire up the latest DirectX 12 game, and the computer instansiates a physics accelerator in part of the FPGA. And then you fire up Matlab for some afternoon fluid dynamics simulation work, and wouldn't you know, the FPGA now provides an array of accelerators tailord to solve your particular matlab equations in hardware... Endless possibilities!

Well, it's not quite reality just yet :) but I think it's a very interesting research area.

Oh and by the way, someone asked about a hardware/FPGA community; if you haven't already you could check out opencores.org although many of the cores are written in RTL Verilog which can be a bit of an "eye sore" to read (IMHO).

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buserror
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Posted by buserror: Mon. Oct 22, 2007 - 11:53 PM
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I checked fpga4fun and opencores, but they both looks like some sort derelict zone. Opencores has bits and pieces, but also lots of cores that are empty, not in cvs, etc.

Maybe my expectations are a bit too high, after 'freaks..

I've ran into a problem actualy, I'm trying to figure out how to do tristate pins/signals. I understood that setting an inout signal to 'Z' and reading it /ought/ to work as I understand it.. however it confuses the simulator. Can it work ?

Right now I had separated the pins to a in and a out, separate, and use a mux in the test harness to mix them... not ideal.

Also, it seems as if "...after X xx;" statements are ignored in process/begin/end sequencial blocks, for the test harness (I know that would't go on the silicon)...

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outer_space
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Posted by outer_space: Tue. Oct 23, 2007 - 02:22 AM
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Breaks my heart atmel can't do fpslic affordably.

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letcat
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Posted by letcat: Tue. Oct 23, 2007 - 04:37 PM
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Buserror, are you trying to do tristate internal signals "on chip" or only on external signals (pads)?
On-chip tristate-busses/signals are NOT recommended design practice and may not be supported by your FPGA or silicon technology. Use seperate read & write busses instead internally (see the ARM AMBA bus or Opencores' Whishbone for example).

Tristateable external pads could be written as: 

entity toplevel is
 port (
  zpin : inout std_logic;
  ..
 );
end entity toplevel;

architechture ...
 signal my_output_signal, my_input : std_logic;
 signal my_output_enabel :std_logic;
 ..

 my_input <= zpin;
 zpin <= my_output_signal when my_output_enable = '0' else 'z';

For testbench delays you could use the WAIT instruction, for example:
WAIT FOR xx ns; WAIT UNTIL signal = state; or WAIT ON signal;

WAIT ON and WAIT UNTIL doesn't work for variables.

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buserror
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Posted by buserror: Tue. Oct 23, 2007 - 06:22 PM
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Thanks letcat, thats how I had instinctively solved the problem somehow.

I had a close look at the FPGA C Compiler that looks like a potentialy really cool thing, but at this stage it's quite unusable; it requires an old version of the Xilinx tools etc. I've bookmarked it tho, it could be very interesting if it evolves further.

Otherwise, it's VHDL full steam here. Still using ghdl/gtkwave but I'm cursing gtkwave not to have implemented a "reload" command to re-import the trace file without having to exit/relaunch the app ! Any pointer on a free, light-ish trace viewer ?

Oh, I bought jayjay's PCI card too, looks like a load a fun :=)

And errrr.. I also bought that book : DESIGN RECIPES FOR FPGAS it looks interesting, I'll see if it keeps it's promises when I get it !

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buserror
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Posted by buserror: Wed. Oct 24, 2007 - 02:05 PM
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As a followup, I just found out that the gtkwave with debian & kubuntu use version 3.0.x; the most recent gtkwave is 3.1.1 and has the reload-file feature.

Rebuilt from source... and Total Bliss :D

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Bronze MarkJohanEkdahl
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Posted by JohanEkdahl: Wed. Oct 24, 2007 - 07:20 PM
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buserror!

Thanks for posting the code, but I was hoping that you'd be able to zip up the whole project and attach it to a post here. Slowly, slowly I am moving forward in my FPGA endeavours. Last night I took a small demo project for a Diligent board and loaded it in the Xilinx ISE WebPack software.

Reading and studying VHDL code is the least difficult part for me right now, much thanks to the excellent "Shock and Awe Tutorial" that was linked to here. It's the rest of the design process that puzzles me the most for the moment. The Diligent demo was in an old project format and was converted when loaded, and that might have added to my confusion. The things that I'm wrestling with right now is
- The overall workflow/process using the ICE WebPack, and
- Specifically how you assign physical pins to "signals".

I was hoping that the smallest possible ICE WebPAck project done with a recent version might help me understand this, so if you could zip up your blinky and post it I would be very greatful!

Time to read up on the ICE WebPack online help. Again - last time around I was far from impressed.

Aside & Note to self: Now that you re-experience the feeling of complete and utter FPGA noobness, memorize it and recall the next time you are talking to a AVR noob. :oops:

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here. 

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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jaydhall
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Posted by jaydhall: Thu. Oct 25, 2007 - 03:03 PM
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Have you visited this site?
http://www.pldesignline.com/
I am starting to do a bit more in FPGA's myself. Thanks for the articles and books you recommended.

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buserror
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Posted by buserror: Sat. Nov 3, 2007 - 11:28 AM
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@jaydhall: thats for that link, theres sone 'high flyer' information there !

I found a forum that looks populated and active. Nowhere near as active as 'freaks but here we go...

I got some very cheap XC9536 CPLDs on ebay (about £15 for 40) so I explored a bit what amount of logic I can fit in there. it's quite reassuring because these are small packages (same package as a Mega644 TQFP) and easy to integrate (easy PSU and clocking) so they will be the ideal companions for any of my next AVR boards :D

Oh, there is also Amontec VHDL Memo that is a quite compact/dense vhdl reference, for when I doubt at the syntax. The Syntax is sinking in, I can almost program 'fluently' without needing to refer to the syntax sheet too often :D

And I received jayjay's board, and found a PCI interface 'core' that I can even understand :-) need to convert to to vhdl and try it out :D

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outer_space
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Posted by outer_space: Mon. Nov 5, 2007 - 02:36 AM
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How do you like the CPLD compared to a fpga? What do you want to do with CPLD? These things are forcing me to deal with finer pitch than soic making my eyes hurt.

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buserror
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Posted by buserror: Mon. Nov 5, 2007 - 09:23 AM
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Well you program the CPLD the same way as the fpga, but with simpler logic of course.
The 'good thing' is that they don't need an external memory to store the configuration (they use built in flash) and only need one power supply (two if you want the IOs to run a different one).
So they are a lot easier to integrate on a 'hobby' board, but still provide great advantages like being able to do more or less any serial protocol (uart, spi, i2c etc) and/or doing mux/demux, pwm, level translations, replace groups of 74's etc.

For soldering, Use the Paste, luke :D

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buserror
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Posted by buserror: Tue. Nov 27, 2007 - 12:50 AM
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Seems Xilinx released a new kit for microblaze. it's this board (with a XC3S1600E monster) for $600; but whats interesting is that it /includes/ the EDK from what I can read, thats quite a saving it seems...
Or am I missing something obvious ?

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