ATtiny1616 -> Releasing WOx from TMRD

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#1
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Pin PC1 I have set as an output. As this is is also controlled by TCD I've ensured the FAULTCTRL register for that pin is disabled.

 

TCD0.FAULTCTRL = 0;

PORTC.DIRSET = 1 << 1;

 

I noticed there is only 2.1v at the pin and a scope showed that the pin has not been released from TMRD (I have a 2MHz 50% duty going). Microchip stated in a support ticket that is can be released for general IO usage?

 

Cheers,

 

Andrew

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Last Edited: Wed. Sep 30, 2020 - 08:22 AM
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Protected register This is not accessible.

TCD0.FAULTCTRL = 0;

 

Please try this.

_PROTECTED_WRITE (TCD0.FAULTCTRL, 0);

 

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Found it, another MCC bug. ON reset it uses the FUSES value. Unsure why but from what I'm seeing it overrides the FAULTCTRL values (which makes me wonder if I can turn any on after setting FUSES.TCD0CFG to 0 but that would then make FAULTCTRL truly pointless).

FUSES = 
{
    .APPEND = 0,
    .BODCFG = ACTIVE_SAMPLED_gc | LVL_BODLEVEL7_gc | SAMPFREQ_1KHZ_gc | SLEEP_ENABLED_gc,
    .BOOTEND = 0,
    .OSCCFG = FREQSEL_20MHZ_gc,
    .SYSCFG0 = CRCSRC_NOCRC_gc | RSTPINCFG_UPDI_gc,
    .SYSCFG1 = SUT_64MS_gc,
    .TCD0CFG = FUSE_CMPAEN_bm | FUSE_CMPBEN_bm | FUSE_CMPCEN_bm | FUSE_CMPDEN_bm,
    .WDTCFG = PERIOD_OFF_gc | WINDOW_OFF_gc,
};

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Please read the data sheet carefully.
.TCD0CFG is only loaded at boot time.
Subsequent changes are at your disposal.

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_PROTECTED_WRITE

That'll be it, 22.3.7. Wish they'd mentioned it in main 22.3.2.7 Output Control section, until you mentioned it I didn't know it existed!

Also MCC isn't using _PROTECTED_WRITE (so this is the bug), if it had I'd have caught it.

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N/A

Last Edited: Tue. Sep 29, 2020 - 12:30 PM
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The existence of _PROTECTED_WRITE is to guarantee the cycle.

Otherwise no one will use it.
I have never been betrayed by _PROTECTED_WRITE.

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I've confirmed it, this doesn't work.

 

    _PROTECTED_WRITE(TCD0.FAULTCTRL, TCD0.FAULTCTRL | TCD_CMPAEN_bm);
    _PROTECTED_WRITE(TCD0.FAULTCTRL, TCD0.FAULTCTRL | TCD_CMPBEN_bm);
    _PROTECTED_WRITE(TCD0.FAULTCTRL, TCD0.FAULTCTRL | TCD_CMPCEN_bm);

 

Also tried

 

    uint8_t v = TCD_CMPAEN_bm | TCD_CMPBEN_bm | TCD_CMPCEN_bm;
    CPU_CCP = CCP_IOREG_gc;
    TCD0.FAULTCTRL = v;

 

So far I'm unable to override the FUSE set values.

 

I have found however if I change the FAULTCTRL before initialising they work. Afterwards turning TCD0 off and on doesn't apply the new values.

    TCD0_Initialize();
    
    TCD0.CTRLA &= ~TCD_ENABLE_bm;

    CPU_CCP = CCP_IOREG_gc;

    TCD0.FAULTCTRL = TCD_CMPAEN_bm | TCD_CMPBEN_bm | TCD_CMPCEN_bm;
    
    TCD0.CTRLA |= TCD_ENABLE_bm;

 

Last Edited: Tue. Sep 29, 2020 - 10:32 PM
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I don't know what's going on with you.
My device is obedient to change.

 

This reply has been marked as the solution. 
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It's the ordering of the STATUS bit, I didn't realise there were sync patterns to look at. That's the second time in the datasheet one section has made no reference to another critical section.

 

Are you using a simulator? It would explain why it's working there but not on chip.

 

This works.  :)

 

    TCD0.CTRLA &= ~(TCD_ENABLE_bm);
    while(!(TCD0.STATUS & TCD_ENRDY_bm)); // must wait here
    CPU_CCP = CCP_IOREG_gc;
    TCD0.FAULTCTRL = TCD_CMPAEN_bm | TCD_CMPBEN_bm | TCD_CMPCEN_bm;
    TCD0.CTRLA |= (TCD_ENABLE_bm);

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# 9 is not a simulator.
I confirmed using a real tiny1616.

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Strange, yours didn't work for me as the status check is in the wrong place. TCD0.CTRLA enable bit is unprotected.