Something seems to be different with the AVR-Dx protection diodes. Why is their voltage drop so low, and current rating so large? Are they some kind of Schottky diodes?
edit: no, I measured with a multimeter and they are regular diodes, so IDK why the datasheet says says "VDD + 0.3V" instead of "VDD + 0.5V" as in normal AVRs.
Posted by Brian Fairchild: Tue. Sep 15, 2020 - 02:24 PM
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El Tangas wrote:
edit: no, I measured with a multimeter and they are regular diodes, so IDK why the datasheet says says "VDD + 0.3V" instead of "VDD + 0.5V" as in normal AVRs.
At higher temperatures the voltage drop will be lower so maybe that figure is to cover the whole operating range?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
Dear Microchip, please may we have one with an on-chip CAN controller peripheral ? Pref in a thru-hole package. Then I can finally tell my PIC-bothering friends to STFU :)
please may we have one with an on-chip CAN controller peripheral ? Pref in a thru-hole package. Then I can finally tell my PIC-bothering friends to STFU :)
pcb files are free for the download, make your own.
I may have 'borrowed' elements of that precise design a couple of years back**. I really need on-chip CAN in a DIP package, for which PIC has several options. Many of my designs' users are averse to surface mount assembly. And the AT90CAN is a rather old and expensive part compared to the devices on this thread.
** which is how I know that the ICSP interface uses the UART pins and not the usual SPI ones.
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
Corrected CDC RX and TX pins in the “On-Board Debugger Connections” table. Corrected function description in the “Crystal Connections” table. The “Crystal Connection and Cut Straps” image is updated.
Kyoto, Japan and Santa Clara, CA, Sept. 24, 2020 (GLOBE NEWSWIRE) — ROHM announces the availability of BM1ZxxxFJ, integrated zero cross detection IC series, optimized for home appliances such as vacuum cleaners, washing machines, and air conditioners.
...
Key Features
[10mW and reduced component count, increased reliability and more precise, near replacement of current ZCD, voltage clamp]
Availability: In Mass Production
Pricing: From 0.98USD/sample (excluding tax)
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6 models are offered to ensure compatibility with a wide range of home appliances.
To use your own AVR128DA48 Curiosity Nano with the Medium One IoT Platform, check out our step-by-step article that walks you through the entire process of:
Microchip has released a new Product Documents for the AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarifications of devices. If you are using one of these devices please read the document located at AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarifications.
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Description of Change: Initial release of this document with Silicon die revisions A4 and A5.
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Estimated First Ship Date: 20 Oct 2020
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Revision History:
August 27, 2020: Initial document release October 14, 2020: Re-issued Errata document PCN to specify the silicon die revisions A4 and A5.
Added errata:
1) Device: Increased Current Consumption May Occur When VDD Drops 2) CLKCTRL: The PLL Will Not Run When Using XOSCHF With an External Crystal 3) TCB: CCMP and CNT Registers Operate as 16-Bit Registers in 8-Bit PWM Mode 4) TCD: Asynchronous Input Events Not Working When TCD Counter Prescaler is Used and CMPAEN Controls All WOx For Alternative Pin Functions
Updated errata: 1) CCL: The CCL Must be Disabled to Change the Configuration of a Single LUT and The LINK Input Source Selection for LUT3 is Not Functional on 28- and 32- pin Devices 2) ZCD: All ZCD Output Selection Bits are Tied to the ZCD0 Bit
Added data sheet clarification: Added Typical Characteristics section with additional plots for OPAMP peripheral.
Addressing this challenge through a focus on increased microcontroller (MCU) integration, Microchip Technology Inc. (Nasdaq: MCHP) today announced the PIC18-Q41 and AVR DB MCU families that are the first to combine advanced analog peripherals and multi-voltage operation with inter-peripheral connections for increased system integration and reduced signal acquisition times, and offer the convenience and efficiency of operating in a single design environment.
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Mixed-signal IoT systems often include multiple power domains, and the AVR DB MCU simplifies the challenges of these designs while reducing cost by integrating true bi-directional level shifters. This feature lowers cost in a wide range of applications including automotive, appliances, HVAC and liquid measurement. The addition of three independent and highly configurable Op Amps, a 12-bit differential ADC, 10-bit DAC, three zero cross detectors and Core Independent Peripherals (CIPs) makes the AVR DB MCU ideal for virtually any application involving analog signal conditioning and processing functions.
Development Support
...
In addition to MCC, the AVR DB is supported by Atmel START, Atmel Studio and third-party tools such as IAR and the GCC C compiler. MCC and START help analog and digital designers easily configure an Op Amp system for various typical use cases through a graphical user interface with no coding required.
Both MCU families offer a compact, cost-effective development board with programming and debugging capabilities: the PIC18F16Q41 Curiosity Nano Evaluation Kit (EV26Q64A) and the AVR DB Curiosity Nano Evaluation Kit (EV35L43A). Quick start guides for the PIC MCU and the AVR MCU are available to start projects immediately.
Pricing and Availability
The PIC18-Q41 and AVR DB MCUs are offered in a range of memory sizes, packages and price points. The PIC18-Q41 pricing starts at $0.65 in 10,000-unit quantities. The AVR DB pricing starts at $0.95 in 10,000-unit quantities.
The PIC18-Q41 and AVR DB MCUs are offered in a range of memory sizes, packages and price points. The PIC18-Q41 pricing starts at $0.65 in 10,000-unit quantities. The AVR DB pricing starts at $0.95 in 10,000-unit quantities.
...
The PIC18-Q41 are interesting reading, and overlap somewhat with the 14p and 20p versions of the AVR DD family.
PIC18-Q41 are 64MHz and have opamps and comparators, whilst AVR DD is only 24MHz.
PIC18-Q41 PLL spec is a little confusing, as it specs
PLL Output Frequency Stability -0.25 — 0.25 %
so maybe that's not a true Analog PLL/VCO at all, but instead a digital locked scheme that uses the RC oscillator trim bits to wobble about an average ?
PIC18-Q41 are 64MHz and have opamps and comparators, whilst AVR DD is only 24MHz.
IIRC, PICs require four cycles per instruction whilst AVRs are as low as one (due to the instruction pipeline, etc). So a 64MHz PIC is equivalent to a 16MHz AVR.
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
Posted by 12oclocker: Tue. Oct 27, 2020 - 05:57 AM
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Headsup.. Parametric search on microchip site does not correspond to datasheet for this series on many of the features. Makes parametric search worthless unfortunately.
Also... regarding errata "The CCL Must be Disabled to Change the Configuration of a Single LUT"...
I cant believe this is not fixed, I reported this when CCL on TinyAvr1 and TinyAvr0 was released years ago. They must have copied and pasted old die code/verilog/vhdl or something into the new design. Very disappointing, I remember working around that issue was a pain.
AVRs will look bad in terms of ISR latency until Microchip adopts a recent version of avr-gcc with the ISR prologue/epilogue fix (v8+ IIRC).
If you want low latency then assembler is probably mandatory. Using C risks creating problems that can be difficult to test for.
To be honest I don't find these kinds of comparisons very useful. Interrupt latency depends a lot on other factors like if you have variable execution time instructions, or how fast you can wake up from sleep modes, what oscillators are available, what your maximum clock rate is etc.
Performance wise you are often interested in power consumption too. Something may take fewer cycles but does it use more energy? Can you just crank the clock rate up to get the speed you need?
I'm uneasy about how Xmega seems to have been purged from the parametric search and most of the website. These new parts are nice but not really replacements for Xmega, e.g. no USB.
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
I'm not sure how the benchmark managed to get 23 cycles latency for the tiny85.
That seems longer than I'd expect if the code ends up in-lined in the ISR function, but shorter than I'd expect if there was an additional function call...
Posted by sparrow2: Wed. Oct 28, 2020 - 11:17 AM(Reply to #193)
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It totally depend if how he has made the port part. It's clear that he's not a AVR guy.
but let's say 2 clk for instruction it's executing now, 4 (or is it 3 I don't remember) to push PC etc. 2 for a rjmp, and now a naked ISR would do the port part. (nothing needs to be pushed for simple code like this)
a normal ISR would add:
push r0
push r1
in r1,SREG
push r1
eor r1,r1
so that is 8 clk added
so in all 16 clk should be the number (8 for naked and I guess if ISR is simple the newer GCC's also will do it this way)
so with 23 my guess is that for some reason the compiler has to push 3-4 registers which make it a very clumsy port code!
There is the interrupt call latency too. On AVR it will be 1-3 cycles to finish the current instruction (unless waking from idle in which case it is deterministic) and then 2 to execute the jump instruction at the interrupt vector.
Well, if you are feeling adventurous you can just place your entire ISR at the interrupt vector...
Well, if you are feeling adventurous you can just place your entire ISR at the interrupt vector...
Well, if there is only one ISR I don't see why not.
edit: anyway, the rjmp/jmp indirection costs 2-3 cycles, which is a bit, but not the bottleneck. The main cost is saving/restore context for the main program flow.
This could be solved by introducing an alternate register file and alternate SREG, as other architectures do (e.g. Z80). When an ISR is called, the switch would be automatic, then RETI would undo the switch. Also, a context swap instruction should be added to AVR assembly to allow direct control over the process if needed. From C, this would allow naked ISRs to be used routinely containing C code (the alternate r1 would need to be initialized to zero by initialization code).
Just my humble suggestion to evolve the architecture. This could be added as another interrupt mode; Modern AVRs already have an alternate mode anyway (compact vector table).
Another suggestion is a programmable vector table, the current one is hardcoded but it doesn't necessarily have to be that way.
Something seems to be different with the AVR-Dx protection diodes. Why is their voltage drop so low, and current rating so large? Are they some kind of Schottky diodes?
edit: no, I measured with a multimeter and they are regular diodes, so IDK why the datasheet says says "VDD + 0.3V" instead of "VDD + 0.5V" as in normal AVRs.
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TopAt higher temperatures the voltage drop will be lower so maybe that figure is to cover the whole operating range?
#1 Hardware Problem? https://www.avrfreaks.net/forum/...
#2 Hardware Problem? Read AVR042.
#3 All grounds are not created equal
#4 Have you proved your chip is running at xxMHz?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
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TopHF crystal was not done as DS says...
my projects: https://github.com/epccs
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TopDear Microchip, please may we have one with an on-chip CAN controller peripheral ? Pref in a thru-hole package. Then I can finally tell my PIC-bothering friends to STFU :)
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TopThis is much more BB friendly than a dip chip https://www.sparkfun.com/product...
FF = PI > S.E.T
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Toppcb files are free for the download, make your own.
FF = PI > S.E.T
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TopI may have 'borrowed' elements of that precise design a couple of years back**. I really need on-chip CAN in a DIP package, for which PIC has several options. Many of my designs' users are averse to surface mount assembly. And the AT90CAN is a rather old and expensive part compared to the devices on this thread.
** which is how I know that the ICSP interface uses the UART pins and not the usual SPI ones.
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Topmostly AVR DB in Sept'20 Atmel START
Atmel START Release Notes
"Dare to be naïve." - Buckminster Fuller
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TopAVR® EA Product Brief
"Dare to be naïve." - Buckminster Fuller
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TopHmm, the MHz on these parts is creeping downwards too ?
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TopSo, slightly cut-down Dx series chips.
#1 Hardware Problem? https://www.avrfreaks.net/forum/...
#2 Hardware Problem? Read AVR042.
#3 All grounds are not created equal
#4 Have you proved your chip is running at xxMHz?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
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TopA small 28-Pin AVR-EA has one more, practical Type-A TCA timer than same 28-Pin AVR-Dx. The only advantage I can find... 🤔
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Top"Dare to be naïve." - Buckminster Fuller
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TopSPICE Model for AVR_DB
18-Sep'20
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TopApparently there is also an AVR-DD:
http://ww1.microchip.com/downloa...
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TopAVR-DC? Hmm... or should I say Ω. All AVR are DC.
my projects: https://github.com/epccs
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TopI was wondering about "DC." Perhaps they skipped it for reasons similar to why Microsoft (supposedly) skipped "Windows 9"
In any case, searching Microchip for "DD" was much more productive than searching for "DC" :-)
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Tophttps://www.mouser.com/Search/Refine?Keyword=bm1z0
https://www.mouser.com/Search/Refine?Keyword=bm1z1
"Dare to be naïve." - Buckminster Fuller
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TopThat's a strange part, as it has no mains isolation - so is only suitable for host-side controllers. (and costs more than many MCUs)
Usually vendors make that lack of galvanic isolation very clear, but ROHM were a bit lazy there....
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Tophttps://www.chip1stop.com/USA/en/view/dispDetail/DispDetail?partId=ROHM-0198488&keyword=BM1Z002FJ-E2
AVR32DA28 and extended temperature | Welcome to Microchip Technology | Microchip Technology Inc.
"Dare to be naïve." - Buckminster Fuller
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TopAVR128DB48 Curiosity Nano Evaluation Kit - Microchip Technology | Mouser
"Dare to be naïve." - Buckminster Fuller
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TopAN3664 AVR DA Low-Power Features and Sleep Modes
"Dare to be naïve." - Buckminster Fuller
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TopAh, the low power mode I wrote is the setting item of the oscillator.
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TopAn ESP32 for the Wi-Fi :
"Dare to be naïve." - Buckminster Fuller
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Topedit :
AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarifications
edit2 : PDF
AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarifications
"Dare to be naïve." - Buckminster Fuller
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Top"Dare to be naïve." - Buckminster Fuller
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Top"Dare to be naïve." - Buckminster Fuller
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TopThe PIC18-Q41 are interesting reading, and overlap somewhat with the 14p and 20p versions of the AVR DD family.
PIC18-Q41 are 64MHz and have opamps and comparators, whilst AVR DD is only 24MHz.
PIC18-Q41 PLL spec is a little confusing, as it specs
PLL Output Frequency Stability -0.25 — 0.25 %
so maybe that's not a true Analog PLL/VCO at all, but instead a digital locked scheme that uses the RC oscillator trim bits to wobble about an average ?
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TopIIRC, PICs require four cycles per instruction whilst AVRs are as low as one (due to the instruction pipeline, etc). So a 64MHz PIC is equivalent to a 16MHz AVR.
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Topthough PIC are accumulator-based
P.S.
Would be interesting to update the following to MPLAB XC8 v2 for PIC18-Q41 as that's based on Clang (LLVM)
https://www.eembc.org/viewer/?benchmark_seq=1559
via CPU Performance Benchmark – MCU Performance Benchmark – CoreMark – EEMBC Embedded Microprocessor Benchmark Consortium
"Dare to be naïve." - Buckminster Fuller
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TopI wish they would do some that can operate at 5V and have USB. That's my dream MCU at the moment, 5V and XMEGA architecture with USB.
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TopThere is some interesting benchmarking on this site...
https://dannyelectronics.wordpre...
https://dannyelectronics.wordpre...
...just two examples, there are others.
#1 Hardware Problem? https://www.avrfreaks.net/forum/...
#2 Hardware Problem? Read AVR042.
#3 All grounds are not created equal
#4 Have you proved your chip is running at xxMHz?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
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TopAVRs will look bad in terms of ISR latency until Microchip adopts a recent version of avr-gcc with the ISR prologue/epilogue fix (v8+ IIRC).
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Top"Dare to be naïve." - Buckminster Fuller
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TopHeadsup.. Parametric search on microchip site does not correspond to datasheet for this series on many of the features. Makes parametric search worthless unfortunately.
Also... regarding errata "The CCL Must be Disabled to Change the Configuration of a Single LUT"...
I cant believe this is not fixed, I reported this when CCL on TinyAvr1 and TinyAvr0 was released years ago. They must have copied and pasted old die code/verilog/vhdl or something into the new design. Very disappointing, I remember working around that issue was a pain.
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TopIf you want low latency then assembler is probably mandatory. Using C risks creating problems that can be difficult to test for.
To be honest I don't find these kinds of comparisons very useful. Interrupt latency depends a lot on other factors like if you have variable execution time instructions, or how fast you can wake up from sleep modes, what oscillators are available, what your maximum clock rate is etc.
Performance wise you are often interested in power consumption too. Something may take fewer cycles but does it use more energy? Can you just crank the clock rate up to get the speed you need?
I'm uneasy about how Xmega seems to have been purged from the parametric search and most of the website. These new parts are nice but not really replacements for Xmega, e.g. no USB.
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TopUSB is a medium complexity peripheral (die space, give and take)
AVR MCUs | Microchip Technology
Direct Memory Access | Microchip Technology
"Dare to be naïve." - Buckminster Fuller
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Top#1 Hardware Problem? https://www.avrfreaks.net/forum/...
#2 Hardware Problem? Read AVR042.
#3 All grounds are not created equal
#4 Have you proved your chip is running at xxMHz?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
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TopThank you for I wasn't clear (maybe I need some Grammarly
"Dare to be naïve." - Buckminster Fuller
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Top#1 Hardware Problem? https://www.avrfreaks.net/forum/...
#2 Hardware Problem? Read AVR042.
#3 All grounds are not created equal
#4 Have you proved your chip is running at xxMHz?
#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."
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TopI'm not sure how the benchmark managed to get 23 cycles latency for the tiny85.
That seems longer than I'd expect if the code ends up in-lined in the ISR function, but shorter than I'd expect if there was an additional function call...
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TopAVR® DB Product Brief
"Dare to be naïve." - Buckminster Fuller
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TopMulti-voltage is nice, need to look at the details but it's something I've wanted for a long time.
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TopIt totally depend if how he has made the port part. It's clear that he's not a AVR guy.
but let's say 2 clk for instruction it's executing now, 4 (or is it 3 I don't remember) to push PC etc. 2 for a rjmp, and now a naked ISR would do the port part. (nothing needs to be pushed for simple code like this)
a normal ISR would add:
push r0
push r1
in r1,SREG
push r1
eor r1,r1
so that is 8 clk added
so in all 16 clk should be the number (8 for naked and I guess if ISR is simple the newer GCC's also will do it this way)
so with 23 my guess is that for some reason the compiler has to push 3-4 registers which make it a very clumsy port code!
Edit I forgot to clear r1
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TopThere is the interrupt call latency too. On AVR it will be 1-3 cycles to finish the current instruction (unless waking from idle in which case it is deterministic) and then 2 to execute the jump instruction at the interrupt vector.
Well, if you are feeling adventurous you can just place your entire ISR at the interrupt vector...
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TopWell, if there is only one ISR I don't see why not.
edit: anyway, the rjmp/jmp indirection costs 2-3 cycles, which is a bit, but not the bottleneck. The main cost is saving/restore context for the main program flow.
This could be solved by introducing an alternate register file and alternate SREG, as other architectures do (e.g. Z80). When an ISR is called, the switch would be automatic, then RETI would undo the switch. Also, a context swap instruction should be added to AVR assembly to allow direct control over the process if needed. From C, this would allow naked ISRs to be used routinely containing C code (the alternate r1 would need to be initialized to zero by initialization code).
Just my humble suggestion to evolve the architecture. This could be added as another interrupt mode; Modern AVRs already have an alternate mode anyway (compact vector table).
Another suggestion is a programmable vector table, the current one is hardcoded but it doesn't necessarily have to be that way.
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TopBut this is about how to do it in C.
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TopIt's possible but you would have to write your own startup code. And use lots of compiler specific stuff.
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Top"Dare to be naïve." - Buckminster Fuller
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