Use DFLL48M as base clock?

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Hi,

 

when checking the manual of ATSAMD51G, there is following statement:

7.3.2 Starting of Clocks

Once the power has stabilized and the internal Reset is released, the device will use a 48MHz clock by default. The clock source for this clock signal is DFLL48M, which is enabled after a reset by default. 

When I understand this correct, after start-up DFLL48M  is running as clock source at 48 MHz. But when I have a look into Atmel START, there is no possibility to let this clock run for its own - to let it produce an 48 MHz output, an other clock source is needed.

 

So: how can one set up DFLL48M to be used as base clock which itself does not needs any clock source? The only thing I got working was

 

OSCLULP32K (32 kHz) -> GCG3 (32 kHz) -> DFLL48M (48 MHz)

 

which is really weird and complicated.

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Elmi79 wrote:

So: how can one set up DFLL48M to be used as base clock which itself does not needs any clock source?

 

Select open-loop mode. See section 28.6.4.1 of the datasheet.

 

I'm not sure if Atmel START will allow you to configure open-loop mode or not.

Josh @ CIHOLAS Inc - We fill the gaps from chips to apps

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In Atmel START (and therefore in my code) Open Loop Mode is already selected. But there is still a clock source mandatory, either an external clock (which does not exists in my case) or one of the Generic Clock Generators (which I want to get rid of)...

 

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Not everything in START is gospel.  I'd have to read the datasheet to be sure but I believe it can be done.  That said I looked at DFLL48 on a spectrum analyser once and other than slaved to USB it is quite unfortunate.

jeff

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Looking at SAMD51 datasheet it says for reset.

 

13.7

Clocks after Reset

On any Reset the synchronous clocks start to their initial state:

•

DFLL48M is enabled and configured to run at 48MHz

•

Generic Generator 0 uses DFLL48M as source and generates GCLK_MAIN

•

CPU and BUS clocks are undivided.

 

From this I gather that Generic Generator 0 is ready to be piped to peripheral upon reset.

 

But why is "DFLL48 input clock source"   itself a peripheral that is by default disabled upon reset. 

 

14.8.4

Peripheral Channel Control

Name:

PCHCTRLm

Offset:

0x80 + m*0x04 [m=0..47]

Reset:

0x00000000

Property:

PAC Write-Protection

 

 

 

 

 

 

Thanks from Verrrrryyyyy confused.

 

 

 

 

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The DFLL48M runs in open loop mode by default (after reset), no reference clock is needed.

Check  "28.6.4.1 Basic Operation".

/Lars