Only SPI modes 0 and 1 supported by Attiny84 USI?

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Just now reading more fine print in the ATTiny84 spec.  I think I can only do SPI slave in modes 0 or 1 using the USI module.

 

Seems that way after reading AVR319 too.

 

It's not a show stopper, but the SPI master is also communicating with a device using mode 2.  So, I'll have to dynamically change the SPI on the master device (rpi), when I want it to communicate with my Attiny84.

 

Just looking for a confirmation of that--(or not).

 

Thanks!

Last Edited: Wed. Sep 29, 2021 - 08:05 PM
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Changing SPI on the fly is not a big deal. I have a mico-SD card and an accelerometer on the same SPI bus and they are in different modes.

 

Fortunately, the master knows which mode to use just as it knows which chip select line to assert.

 

Jim

 

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Have just barely started on  RPi. Have not yet learned how to deal with SPI, at all.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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You should have full mode choice if you bit-bang SPI on the Tiny. Just be aware of slower max SPI clock rate (than hardware).

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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I have an ATTINY861 with USI hung on an ATMEGA1284's SPI buss with a bunch of other things. I am concerned that USI is NOT compatible with SPI in either mode 1 or 0.

Look at waveform diagram 13.3 for USI 3-wire mode in ATTINY861 spec and compare with the same thing for SPI in figre 16.4 of the ATMEGA1284 spec. 

In SPI mode 1 in figure 16.4, the clock starts low. The first rising edge is ignored and the output data is good on the first falling edge.

Compare with figure 13,3 for USI: In the mode starting with clock low, the data is sampled on the first rising edge. Exactly the opposite.

Now pretty much everything esle in the world actually uses the other clock polarity: Clock starts high, the firrt falling edge is ignored, and data is sampled

on the rising edges. In figure 16.4 fo the SPI spec, this called mode 3 ?

 

Is the USI diagram wrong or is this a big blunder ?

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On re-checking it seems that, whatever mode it is called,: the mode that starts with clock low and samples data on the first rising edge is compatible with both SPI and USI and that is what other devices seem to use too.

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Although I have not confirmed this on hardware yet (I will be using an ATtiny84), the datasheet leaves me thinking that the USI Three-wire mode supports SPI modes 0 and 2, rather than 0 and 1. See my post here. I will report back after testing hardware.

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Reporting back... I tested USI/SPI mode combinations (see post) on hardware, and discovered that  USI Three-wire slave modes, USICS1:USICS0=1:1 and 1:0, are compatible with only SPI master mode 1 (CPOL=0, CPHA=1and mode 3 (CPOL=1, CPHA=1), respectively.

Last Edited: Tue. Jun 23, 2020 - 11:06 AM