Atmega328PB Programming troubles using SPI with ATMEL-ICE

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I am working on a board using the ATmega328P. It is not complicated, just reading 13 tactile switches ringing a buzzer, dimming some LEDs and keeping track of the battery charger and the voltage level. I had the boards made by JLCPCB and took advantage of their assembly service to add the components on the boards. Unfortunately due to a miscommunication on my side, I added the ATMega328PB to the BOM instead of the 328P that I used to base the design on. Anyway, after an inspection of the board and reviewing the 328PB datasheet I could not find a reason why the 328P design wouldn't work so I soldered the 6 pin ICSP header and prepared to load the prototype firmware using the ATMEL-ICE. My first step was to attempt to change the fuses to prepare the MCU for the firmware written in AS7, so I switched the device from 328P to 328PB but ran into the message indicating that the programmer could not establish a connection with the SPI interface. I checked power, cables, connector polarity, etc, even tried connecting to the breadboard 328P which did connect (although I got the expected signature mismatch message). I considered that the IC was bad.

 

On a moment of frustration and out of desperation I switched the interface from SPI to debugWire AND IT CONNECTED! So I am able to compile and link, then upload the firmware to the MCU using debugWire. I can even debug the program, which has been helpful in moving along the testing but I cannot change the fuses nor program the EEPROM with the configuration tables I need for the firmware.... I must add that I CAN exit debugWire mode normally from the AS7 interface, no errors reported and I believe this succeeds because when I try to go back to debugging I will receive the warning about enabling the DWEN fuse bit. However I CANNOT get the SPI interface to connect.

 

I have embedded here the schematic and pictures of the copper on the board in hopes that someone spots something indicating a wiring issue that would lead to conflicts with the SPI programming mode. The schematic is for the 328P but the difference with the 328PB is that pins 3 and 6 are IO pins that now happen to be connected to GND and VCC directly. I have 5 of these boards, I tried a second one with similar results. My next step is to give it a go with the high voltage programmer just to see if it will change anything but I wanted to ask others for a second set of eyes and any advice in case someone had run into this case before.

 

Thank you for your time.

Copper bottom

Copper top, ICSP connects on this side.

 

 

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My first step was to attempt to change the fuses to prepare the MCU for the firmware written in AS7, so I switched the device from 328P to 328PB

 

Why/what  fuses would you be changing??...leave them factory set, especially for now & at least see if you can do ISP. If anything, you'd need to compile your program for the chip being used...the 328PB ...make sure your programmer is "set" for 328PB !!

Be careful your PB program does not conflictingly output onto the PE lines, since your non-PB layout board ties them to either gnd or Vcc...a driven conflict will appear as a "short" 

 

 

There was just a post about mega328pb programming madness...

see if any of this might help, there are some tidbits there

 

https://www.avrfreaks.net/forum/atmega328pb-problems?skey=mega328pb

 

 

Don't connect AREF to power, you need a cap to gnd.  You can supply an analog ref there, or if you like, internally select the supply voltage.  If you do apply a voltage, be careful with the pin settings to avoid an internal short (or easier to not apply a voltage to aref).

Newer AVRs' have "fixed" this semi-malady.

 

I certainly hope your ADC pin24 doesn't go directly to your battery, include at least a 1k resistor, so you don't accidentally blow the AVR.  Beyond that you prob want an RC filter, maybe zener or ESD clamp, etc.

Add a 10k pullup to your reset line

 

The bottom layer should be completely redone...you can probably put all (or 99.8%) of your traces on the component layer & keep the other as just a clean gnd plane (sheet of copper).  You might need a little  1/4 inch piece of trace here and there (maybe to dip under  a trace), but even that is doubtful for a board this bare.  Take time to avoid making a twisted mess (too easy to do) & you'll avoid all kindsa trouble.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sat. May 9, 2020 - 07:11 AM
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What else is connected to your ISP pins?

#1 Hardware Problem? https://www.avrfreaks.net/forum/...

#2 Hardware Problem? Read AVR042.

#3 All grounds are not created equal

#4 Have you proved your chip is running at xxMHz?

#5 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand."

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avrcandies wrote:

My first step was to attempt to change the fuses to prepare the MCU for the firmware written in AS7, so I switched the device from 328P to 328PB

 

Why/what  fuses would you be changing??...leave them factory set, especially for now & at least see if you can do ISP. If anything, you'd need to compile your program for the chip being used...the 328PB ...make sure your programmer is "set" for 328PB !!

Be careful your PB program does not conflictingly output onto the PE lines, since your non-PB layout board ties them to either gnd or Vcc...a driven conflict will appear as a "short" 

 

 

There was just a post about mega328pb programming madness...

see if any of this might help, there are some tidbits there

 

https://www.avrfreaks.net/forum/atmega328pb-problems?skey=mega328pb

 

 

Don't connect AREF to power, you need a cap to gnd.  You can supply an analog ref there, or if you like, internally select the supply voltage.  If you do apply a voltage, be careful with the pin settings to avoid an internal short (or easier to not apply a voltage to aref).

Newer AVRs' have "fixed" this semi-malady.

 

I certainly hope your ADC pin24 doesn't go directly to your battery, include at least a 1k resistor, so you don't accidentally blow the AVR.  Beyond that you prob want an RC filter, maybe zener or ESD clamp, etc.

Add a 10k pullup to your reset line

 

The bottom layer should be completely redone...you can probably put all (or 99.8%) of your traces on the component layer & keep the other as just a clean gnd plane (sheet of copper).  You might need a little  1/4 inch piece of trace here and there (maybe to dip under  a trace), but even that is doubtful for a board this bare.  Take time to avoid making a twisted mess (too easy to do) & you'll avoid all kindsa trouble.

 

Thanks avrcandies, I will check the post as soon as I can. I have not changed the fuses, but I was planning on doing so to switch to the external clock source and remove the clock divider bit. As I ran into trouble I did just as you say and set the fuse changes on the back burner for now. Especially since I can't even read them to see what they are!

 

I should add that I have not connected the external resonator yet to the board since I expect the chip to be set to use its internal oscillator.

 

I'll double check the PE lines as you mention, my understanding is that the IO ports are defaulted to Hi-z on power up but I will look into it.

 

I do appreciate the feedback about the board design. Let me think about it a bit more and if you don't mind maybe I can send you a separate message to ask some followup questions about your suggestions.

 

Last Edited: Sat. May 9, 2020 - 03:26 PM
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Brian Fairchild wrote:

What else is connected to your ISP pins?

 

Brian,

 

The traces on the ISP pins go to the front side of tactile switches that connect the signal to ground when pressed. I have checked the switch connections, there are no shorts there, in fact through the DW interface I loaded up the firmware to test them and I can see the switch presses behaving correctly both in the debugger and via toggling an LED on a separate pin. I think I know what you are getting to and yes, from prior head-banging-on-desk experience I made sure not to put something that would sag the SPI signals on those lines when programming :).

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I do appreciate the feedback about the board design. Let me think about it a bit more 

Here is a PCB I did a while back...There are about 100+ components on the top layer.  Some of it is high current stuff (switchmode driving).  You can see the bottom layer is fairly clean without too many breaks & a solid gnd plane. I circled the ISP connector.  You can do pretty well with 2 layers, if you take your time to do so.

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sat. May 9, 2020 - 05:54 PM
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CapacitiveSmoke wrote:
remove the clock divider bit
There is not really a need to do that as in can be done in the software during setup by writing the CLKPR register. Sometimes, it is nice to start slow and then set clock divider to 1 once some self-checking is complete. YMMVwink

David (aka frog_jr)

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frog_jr wrote:

There is not really a need to do that as in can be done in the software during setup by writing the CLKPR register.

Good point, I'll incorporate this idea into my work flow.

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avrcandies wrote:

Here is a PCB I did a while back...There are about 100+ components on the top layer.  Some of it is high current stuff (switchmode driving).  You can see the bottom layer is fairly clean without too many breaks & a solid gnd plane. I circled the ISP connector.  You can do pretty well with 2 layers, if you take your time to do so.

Regarding the layout of the PCB and without meaning to question your wisdom, what is the reason you recommend I move the components to the top side? The reason these components are on the bottom is because mechanically they interfere with the case. However the buttons and LEDs are on the top, just on a different part of the board not shown in the screen clippings I included.

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what is the reason you recommend I move the components to the top side?

Either PCB side is perfectly fine.  Very often & historically, the "top side" IS the side with the components (or perhaps called the "component side")...look at any old TV or VCR, etc.   Now with the days of SMD, you can have components on both sides....so then which is the component side (or even the top side)?    PCB programs may refer to the TOP layer & BOTTOM layer, or use numbering. 

Maybe call one side Lucy & the other Snoopy.  Which way is up, anyhow?

 

The main point is, with some elbow grease you can have a significant plane, not chopped & smashed to bits.  The width of the plane is what gives it its benefit...both from very low resistance, and often more importantly, low inductance standpoints. 

Any incidental cut/slices of the plane should be as short as possible (unless you are trying to make a split plane/star connection).  When I see a slice in a plane, I say ouch, like I just got a paper cut & that increase my resolve to remove it.

 

I'll double check the PE lines as you mention, my understanding is that the IO ports are defaulted to Hi-z on power up but I will look into it.

Yes, this is just a warning in case you suddenly decided to use them & forget your PCB had these pins "welded" to Vcc and GND.  

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sat. May 9, 2020 - 07:05 PM
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avrcandies wrote:

Either PCB side is perfectly fine.  Very often & historically, the "top side" IS the side with the components (or perhaps called the "component side")...look at any old TV or VCR, etc.   Now with the days of SMD, you can have components on both sides....so then which is the component side (or even the top side)?    PCB programs may refer to the TOP layer & BOTTOM layer, or use numbering. 

Maybe call one side Lucy & the other Snoopy.  Which way is up, anyhow?

 

I hear you on the top/bottom point. The way this board is mounted the "top" faces the user, has the buttons, an LCD, etc. The "bottom" has most of the components because of the mechanical interface.

 

avrcandies wrote:

The main point is, with some elbow grease you can have a significant plane, not chopped & smashed to bits.  The width of the plane is what gives it its benefit...both from very low resistance, and often more importantly, low inductance standpoints. 

Any incidental cut/slices of the plane should be as short as possible (unless you are trying to make a split plane/star connection).  When I see a slice in a plane, I say ouch, like I just got a paper cut & that increase my resolve to remove it.

 

I make no presumption that I have any skill in doing PCB layout, or even building circuits. I mess around with these things as a hobby and try to apply what I learn from my mistakes and the wisdom of other folks to the projects I embark on. I understand the benefits of the solid ground plane, especially in this case since I am not trying to separate ground references and I expect it will help with EMI since this will be a handheld product. I did think that there was some segmenting of the plane which is why I added the vias under the IC to try to extend it by going to the other side. In fact, there's a ton of vias. That being said and as I mentioned before, I am no expert at laying out a board so I appreciate the feedback on what you see.

 

At the risk of further exposing my level of inexperience, but mostly for context and reference, here is a snapshot of the full board, top (red) and bottom (blue). You may notice what I may consider to be sizable ground planes, but surely there's much to improve :). Comments are welcome.

 

 

 

avrcandies wrote:

Yes, this is just a warning in case you suddenly decided to use them & forget your PCB had these pins "welded" to Vcc and GND.  

 

Understood. I am already considering switching to the 328PB and making use of those pins in the next revision.

 

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The fact that debugWire works means that the fuse could be rewritten at least once.

Did you perform "Debug"-> "Disable debugWIRE and Close" operation to disable debugWire?

It seems that a resistor is connected to MOSI / MISO / SCK. Did you try removing it?

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Now that you show the whole board, its easier to see what's going on and things actually look somewhat better...you have the makings of an "layered" gnd plane...part on top & part on bottom...this is a slight step down (nothing beats a solid plane), but this can be good when it's well done...the important thing is to have lots of connections joining them & you do have a ton...so great (I've seen where folks have 10 joining holes for the entire board---poor poor!!).  You are effectively trying to create on big sheet with a little bit on top and a little bit on the bottom, etc.

 

The gridded hole pattern was not visible in the original posting, making things seem a lot more iffy.  You do have to be careful to ensure you haven't created "islands" or sections where the plane remains broken...Of course, a plane everywhere is not 100% necessary in the first place ...you can get by with less.  This style take a bit more inspection to see if all is well.   You don't want to accidentally create the weak link in the chain ("B") between two major sections "A" & C", if A/C  need strongly planed together.   Using the interconnecting holes is not quite as good as a full copper, and wavelength can play a factor in determining hole spacing, if things are critical (not here by any means).   Kinda like a 3 foot continuous weld is prob stronger than using 4 bolt holes or even 8 bolt holes. 

 

You might have been able to route many more of the red traces on the blue side ---did you try much of that?  Then, you would have bigger uninterrupted sections of copper...A utopia for electrons!   

Instead of putting a long trace on the red side, draw it on the blue side and if in a jam occurs, just drop down to blue (like a highway overpass) & pop back up to the red.  Little incursions are much preferred over long slices.   Or,even if you have to have a long slice, drop that down for a short bit then pop up so the long slice becomes two half slices with a short gap (the drop).   That's like the U-turn spots along the middle of the highway.  The worst thing is to have a long slice on a gnd plane (non gnd plane, don't care).  

The shorter the gap between holes or these spacings, improves the high freq performance of the plane.  

     

 

With your latest views, things appear much better (though always make your own thorough check & look for gaps---take a walk from point A to B  can you stay on the plane?  How many plane vias (if any) do you take to get there?  How many holes are in parallel (you want many,  like the bolt example).   Hopefully this commentary will be useful when you layout other boards.

 

A good read:   https://www.allaboutcircuits.com/technical-articles/multipoint-grounding-gridded-ground-for-double-sided-pcbs/

Also, here is a bit more info about "gridding":

Rather than place a continuous ground plane across the entire bottom layer, one technique that can be used in a two-layer PCB is gridding. Power and ground traces are routed in a differential manner, mimicking a pair of power lines. Every ground trace can be expanded to fill up as much of the empty PCB space as possible, and all the remaining empty space can be filled with ground pour. This technique will give your two-layer board the same level of noise reduction as a four-layer board.

One other solution is to use two perpendicular grid patterns on both layers, and the grids can be connected with vias at points where the grids cross. This ensures that all sections of the grid remain at nearly the same potential and provides some extra real estate for components on both layers. A potential problem with this design is with routing between grids on a single layer. In this case, a grounded trace can be routed next to a signal trace, where the grounded trace is connected to the ground sections on the opposite layer with vias.

As with many design choices, gridding represents a tradeoff: you get more real estate on your board and can create low inductance current loops with creative routing, but you lose some of the EMI protection provided by a continuous ground plane. The vias required for gridding also act as inductive impedance discontinuities, creating signal integrity problems with high speed signals. Gridding can also form a conductive loop around components, and radiated EMI can induce current in this loop of conductor. A better choice is to place components on one layer above the ground grid on the other layer.

 

To summarize, be careful with gridding. Certain design guidelines will recommend gridding in a two layer board as an alternative to using a continuous ground plane on a single layer. For low speed/low frequency signals or DC boards with sufficient shielding from the chassis, this may be just fine. However, in cases with high speed/high frequency without shielding or an environment with significant radiated EMI, it may be a better idea to sacrifice board real estate and opt for a continuous ground plane on the bottom layer.

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. May 10, 2020 - 06:53 AM
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What is going through the slot? You may want to pull the traces inside and keep a continuous ground around the slot if cables or whatnot go through it. Also, I would do everything I could think of to keep a continuous ground around the outside perimeter on top and bottom. This link shows my latest, it is in no way perfect but does show some ideas to consider.

 

https://github.com/epccs/Gravimetric/tree/master/Hardware

 

I have heard it said that fast-changing current seeks to flow on the plane edge (if it can get there). As a thought experiment consider if the outside edge is continuous how would that edge seeking current get there, I think it flows on the inside edges where the plane is broken up by traces and all the switching rubbish I have crammed onto that imperfect purple PCB puppet (no offence meant to the board maker, they are perfect).

my projects: https://github.com/epccs

Debugging is harder than programming - don’t write code you can’t debug! https://www.avrfreaks.net/forum/help-it-doesnt-work

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This link shows my latest

Very interesting, and I simply must ask...I noticed a lot of "round" pads for the RC passives, rather than the typical rectangular pads (or maybe they aren't so typical !!)   ...do you have any explanation behind those?  Has it worked out good/bad/otherwise?  Did you walk away from RC rectangular pads, never to return?

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. May 10, 2020 - 08:28 AM
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Because I want to...

 

Once upon a time I was a test engineer on an SMD line for about 20 years, I did a lot of failure analysis (it was not fun, I do not want to repeat that). One thing I noticed was that the solder does not want to wet the far corners, I am guessing it has to do with the cohesive force (or something like that).

 

At some point I read IPC-7351B standard:

 

"Also, the usage of oblong, or rounded, land pattern pads is considered advantageous for lead free soldering processes in comparison with rectangular pads, as the oblong shape provides for a pull of the solder on the pad. An exception to this rule occurs when the heel portion of the land pattern has to be trimmed due to the component body standoff being less than the paste mask stencil thickness or the heel having to be trimmed due to “Thermal Pad” interference. In these two cases, the rectangular pad shape is preferred to compensate for the reduction in copper area of the land pattern pad length."

 

Anyway, it is just how I do things, don't get hung up on it.

 

Update: It has been a long time since I messed with a stencil. If I find a stencil shop that I like and they can't do the round corners or they cost extra, I may have to nix the round corners. My understanding is that with laser cutters it is not a problem.

 

update2: I also needed a quick and dirty way to tell if I had looked at the pads and found them to be OK, so it is my approval mark. The PCB pads library is not to be trusted, I suggest verifying each one used, and figuring out a way to to keep track of the ones checked.

 

my projects: https://github.com/epccs

Debugging is harder than programming - don’t write code you can’t debug! https://www.avrfreaks.net/forum/help-it-doesnt-work

Last Edited: Sun. May 10, 2020 - 11:04 PM
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Thanks!...that is an interesting observation...also the cross-check on the libraries is noted...been nearly burned before, using component libraries from various places & finding the footprint completely wrong, or seriously impaired.   

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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kabasan wrote:

The fact that debugWire works means that the fuse could be rewritten at least once.

Did you perform "Debug"-> "Disable debugWIRE and Close" operation to disable debugWire?

It seems that a resistor is connected to MOSI / MISO / SCK. Did you try removing it?

 

I did exit the debugWire mode from the debugging session. That part works well and is part of what confounds me.

The buttons on the front side of the board are an assembly that has the button and 0.1 uF debounce capacitor. However, the buttons sharing the MOSI/MISO/SCK lines are not mounted and instead get debounced in software. Goot call though, I've definitely been burned by this before, or an LED that is set up so the anode faces the MCU pin...

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avrcandies wrote:

Now that you show the whole board, its easier to see what's going on and things actually look somewhat better...you have the makings of an "layered" gnd plane...part on top & part on bottom...this is a slight step down (nothing beats a solid plane), but this can be good when it's well done...the important thing is to have lots of connections joining them & you do have a ton...so great (I've seen where folks have 10 joining holes for the entire board---poor poor!!).  You are effectively trying to create on big sheet with a little bit on top and a little bit on the bottom, etc.

 

Great stuff, thank you so much for taking the time to write this up I'll be studying up on ground planes next.

 

You are correct, this is board does not deal itself with high speed signals and the case I hope to fit it into has good shielding. There is a pad on the red side, to the right of the three holes of the resonator that connects a pogo pin to the shielding on the front cover. The 40 pin vertical header connects a Raspberry Pi Zero W that will piggy back onto the board and I do intend to use the wireless radios on it. I have no idea what level of interference this may create yet, it is next on my testing after making sure the circuit I setup for the board operates as expected as it is.

 

Fortunately in KiCAD the design rules check does a great job of pointing out the places where a ground pour may become isolated by signal traces around it. A routing technique I often use, which I don't claim to be correct, is to do horizontal lines on one side of the board and vertical lines on the other, as much as possible. I have found this tends to minimize the number of vias which has been helpful to me because I mostly mill my own boards. It's in cases like these where I have a much more complex board that I will wait the 2-3 weeks to get one back from a fabricator.

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ron_sutherland wrote:

What is going through the slot? You may want to pull the traces inside and keep a continuous ground around the slot if cables or whatnot go through it. Also, I would do everything I could think of to keep a continuous ground around the outside perimeter on top and bottom. This link shows my latest, it is in no way perfect but does show some ideas to consider.

 

https://github.com/epccs/Gravimetric/tree/master/Hardware

 

I have heard it said that fast-changing current seeks to flow on the plane edge (if it can get there). As a thought experiment consider if the outside edge is continuous how would that edge seeking current get there, I think it flows on the inside edges where the plane is broken up by traces and all the switching rubbish I have crammed onto that imperfect purple PCB puppet (no offence meant to the board maker, they are perfect).

 

Ron, the slot on the board allows the flexible printed circuit of a LCD to reach around back to where a driver board will piggy back to the main PCB. That is what the SMD header on the bottom of the blue side is for. Now that I received these boards I have confirmed that I can reduce the height of the slot which will allow for more space to do what you suggest.

 

That gravimetric board is really cool. Thank you for sharing that and I like your approach for reviewing the component pads. The explanation for how solder wicks better with rounded edges makes sense to me.

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Fortunately in KiCAD the design rules check does a great job of pointing out the places where a ground pour may become isolated by signal traces around it.

Well that's good news for a connectivity perspective!  Keep in mind that having one via is somewhat limiting from an electromagnetic perspective and keeping the inductance low. The width is a critical parameter...wide planes have low inductance.  Consider a solid plane that is 4 inches long and 2 inches wide. Now instead, you cut it in half (2 inches) and connect them together using one via.  A much different physical scenario between them !!!     Probably several vias at least for good rf grounding...though it can approximate the original setup.

Note that if you bring a gnd plane under a very noisy component, that might be beneficial in reducing emissions, but bring that noise into other sections (so some planes will get purposely split).

 

 

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Tue. May 12, 2020 - 05:29 AM
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My possible RF antenna.

 

 

The fast-changing currents will have capacitance and inductance that oscillate at some frequency. How well it emits RF depends on how well it couples with free space (e.g., the impedance matching of that structure). That is what I think is going on, but I am not sure if my thinking it right so maybe someone can correct.

 

One fix option is to move R240 down some and the trace above so the plane fills a connection. I have a million of those problems that need to be found. The small antenna might have high enough frequency to ignore, but I am not sure of the size where I should actually start to worry about it.

 

Sometimes I think of the vias as resistive dissipators that can dampen oscillations, so I'm not going for the lowest inductance and resistance between what is left of my planes. RF circuits need to maintain their impedance characteristics and I think all that stitching helps to do that.

my projects: https://github.com/epccs

Debugging is harder than programming - don’t write code you can’t debug! https://www.avrfreaks.net/forum/help-it-doesnt-work