I'm looking at replacing PIC functionality with the aforementioned chip which is a much better match for my needs. I have one potential show stopper, however.
OUT1: I have a combined AND operation based on a PWM signal and two comparators. I've set this up using LUT0. Easy.
OUT2: I then have a third comparator which needs to latch. In PIC land I used to define a CLC as an SR, or I could use a CWG with auto-restart disabled. But in LUT1 this doesn't seem possible?
Finally, if OUT2=1 then OUT1 must be 0. This condition might be reset by an external condition or I can do it in hardware.
The issue then is that the Attiny's CCL after LUT0 and LUT1. The closest I seem able to get is using a JK, which would work if OUT2 went to the reset and not the K pin, which causes it to goggle instead of holding state 0.
Any ideas or am I out of luck?