SAMD21 STANDBY current draw increases after interrupt. Never returns to lowest.

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Hi,

I am new to the SAMD21 (specfically I am using the SAMD21E18A).  I have developed my own board which I am hoping to power using a 3V coincell.  I have been working on reducing the power consumption to make this possible and using some of the Atmel Application notes I have got the power down to approx 7-8uA.  I have an LED and button on the board.  The button provides an interrupt (LOW LEVEL).

When the program starts I flash the LED before going to into STANDBY.  Pressing the button wakes the processor and I flash the LED again before going back into STANDBY.

Problem is that the current draw when I first power up the board and it goes to sleep (STANDBY) the current draw drops to approx 8uA (nice).  When I press the button the LED flashes once as expected and processor goes back to sleep, but the current draw is now over 900uA, approaching 1mA.  I can continue to press the button and each time the current draw is around 900uA.  It never goes back to the current draw it had after first power up and sleep.

I cannot understand why after pressing the button (interrupt) the current draw never returns to the low level that was shown at power up.

Does anyone have any idea why this is happening?  Any help is appreciated.

Thanks

Mark

 

Below is my sample code and conf_clocks.h (I am using Atmel Studio 7)

/**
 * \file
 *
 * \brief Empty user application template
 *
 */

/**
 * \mainpage User Application template doxygen documentation
 *
 * \par Empty user application template
 *
 * This is a bare minimum user application template.
 *
 * For documentation of the board, go \ref group_common_boards "here" for a link
 * to the board-specific documentation.
 *
 * \par Content
 *
 * -# Include the ASF header files (through asf.h)
 * -# Minimal main function that starts with a call to system_init()
 * -# Basic usage of on-board LED and button
 * -# "Insert application code here" comment
 *
 */

/*
 * Include header files for all drivers that have been imported from
 * Atmel Software Framework (ASF).
 */
#include <asf.h>

/** Function prototypes */
void while_one(void);
void configure_gclk_pin(void);
void configure_power_manager(void);
void turn_off_bod33(void);
void switch_gclkgen_to_peripherals(void);
void disable_cache(void);

#define MAX_GCLK_ID 0x25

volatile bool butPressed;

/**
 * \brief While 1 loop test function
 */
void while_one(void)
{
	while (1) {

	}
}

/**
 * \brief Function to turn of the BOD33 detector.
 *
 * The Configuration described in the Power Consumption section in the data sheet
 * has the BOD33 off this function turns the BOD33 off.
 */

void turn_off_bod33(void)
{
	SYSCTRL->BOD33.reg = 0;
}

/*
 * \brief Function to configure Power Manager (PM)
 *
 * This function configures the PM. The PM controls what synchronous
 * clocks clocks are running and not. This configuration of the PM is the one used in
 * the Power Consumption section in the data sheet. Some of the clocks in the clock masks
 * used here are disabled by default but have been added to give an easy overview of what
 * clocks are disabled and not.
 */
void configure_power_manager(void)
{
	system_apb_clock_clear_mask(
			SYSTEM_CLOCK_APB_APBA,
				(PM_APBAMASK_WDT \
				| PM_APBAMASK_PAC0 \
				| PM_APBAMASK_GCLK \
				| PM_APBAMASK_RTC \
				| PM_APBAMASK_PM \
				| PM_APBAMASK_SYSCTRL \
				/* These clocks should remain enabled on this bus
				| PM_APBAMASK_EIC \
				*/
				));	

	system_apb_clock_clear_mask(
			SYSTEM_CLOCK_APB_APBB,
				(PM_APBBMASK_PAC1 \
				| PM_APBBMASK_DSU \
				| PM_APBBMASK_DMAC \
				| PM_APBBMASK_USB  \
				| PM_APBBMASK_NVMCTRL \
				| PM_APBBMASK_HMATRIX \
				/* These clocks should remain enabled on this bus
				| PM_APBBMASK_PORT \
				*/
				));

	system_apb_clock_clear_mask(
			SYSTEM_CLOCK_APB_APBC,
				(PM_APBCMASK_ADC \
				| PM_APBCMASK_PAC2 \
				| PM_APBCMASK_DAC \
				| PM_APBCMASK_PTC \
				| PM_APBCMASK_AC \
				| PM_APBCMASK_TC7 \
				| PM_APBCMASK_TC6 \
				| PM_APBCMASK_TC5 \
				| PM_APBCMASK_TC4 \
				| PM_APBCMASK_TC3 \
				| PM_APBCMASK_TCC2 \
				| PM_APBCMASK_TCC1 \
				| PM_APBCMASK_TCC0 \
				| PM_APBCMASK_SERCOM5 \
				| PM_APBCMASK_SERCOM4 \
				| PM_APBCMASK_SERCOM3 \
				| PM_APBCMASK_SERCOM2 \
				| PM_APBCMASK_SERCOM1 \
				| PM_APBCMASK_SERCOM0 \
				| PM_APBCMASK_EVSYS \
				| PM_APBCMASK_I2S \
				));

	system_apb_clock_set_divider(
			SYSTEM_CLOCK_APB_APBA,
			SYSTEM_MAIN_CLOCK_DIV_4);

	system_ahb_clock_clear_mask(
				(PM_AHBMASK_USB \
				| PM_AHBMASK_DSU \
				| PM_AHBMASK_HPB1 \
				| PM_AHBMASK_HPB2 \
				| PM_AHBMASK_DMAC \
				| PM_AHBMASK_HPB0 \
				/* These clocks should remain enabled on this bus
				| PM_AHBMASK_HPB1 \
				| PM_AHBMASK_HPB2 \
				| PM_AHBMASK_HPB0 \
				| PM_AHBMASK_NVMCTRL \
				*/
			));
}

void disable_cache(void)
{
	NVMCTRL->CTRLB.bit.CACHEDIS = 1;
	//Readmode settings : 0-3
	NVMCTRL->CTRLB.bit.READMODE = 0;
}

/**
 * This function switches all GCLK outputs to a generator that is
 * configured with a source oscillator. The exception is GCLK_DFLL_REF which is kept running.
 * This function must be called after system_clock_init(). system_clock_init() will normaly
 * be claied in system_init() in asf. If it is not the change will not be aplied.
 * In ASF versions later than 3.19 this will be done automaticlay when system_clock_init() is caled
 * and this function should not be called again as it will only be waisting time.
 */
void switch_gclkgen_to_peripherals(void)
{
	for (int gclk_id = 1; gclk_id < MAX_GCLK_ID; gclk_id++) {
		GCLK->CLKCTRL.reg = (gclk_id << GCLK_CLKCTRL_ID_Pos) | GCLK_CLKCTRL_GEN_GCLK7;
	}
}

#define MY_LED    IOPORT_CREATE_PIN(IOPORT_PORTA, 6) // PA06
#define MY_BUTTON IOPORT_CREATE_PIN(IOPORT_PORTA, 4) // PA04

void button_extint_callback(void)
{
	butPressed != butPressed;
}

#define CONF_CHANNEL 4

void configure_button_extint(void)
{
	struct extint_chan_conf extint_chan;
	extint_chan_get_config_defaults (&extint_chan);

	// configure EXTINT channel
	extint_chan.gpio_pin           = PIN_PA04A_EIC_EXTINT4;
	extint_chan.gpio_pin_mux       = MUX_PA04A_EIC_EXTINT4;
	extint_chan.gpio_pin_pull      = EXTINT_PULL_UP;
	extint_chan.detection_criteria = EXTINT_DETECT_LOW;

	extint_chan_set_config(CONF_CHANNEL, &extint_chan);

	extint_register_callback(button_extint_callback, CONF_CHANNEL, EXTINT_CALLBACK_TYPE_DETECT);
	// Enable the registered callback function for the configured External Interrupt channel
	extint_chan_enable_callback(CONF_CHANNEL, EXTINT_CALLBACK_TYPE_DETECT);

}

int main (void)
{
	butPressed = false;

	/* Configure GCLK and clock sources according to conf_clocks.h */
//	system_clock_init();
	system_init();
	delay_init();
	ioport_init();

	ioport_set_pin_dir(MY_LED, IOPORT_DIR_OUTPUT);

	// Flash LED 3 times before sleeping
	for (int i = 0; i < 6; i++)
	{
		ioport_toggle_pin_level(MY_LED);
		delay_s(1);
	}

	configure_button_extint();

	switch_gclkgen_to_peripherals();

	turn_off_bod33();

	configure_power_manager();

	while (true)
	{
		system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY);
		system_sleep();

		ioport_set_pin_level(MY_LED, true);
		delay_s(1);
		ioport_set_pin_level(MY_LED, false);
	}

	while_one();
}

conf_clocks.h

 

/**
 * \file
 *
 * \brief SAM D21 Clock configuration
 *
 * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved.
 *
 * \asf_license_start
 *
 * \page License
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 *    this list of conditions and the following disclaimer in the documentation
 *    and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an
 *    Atmel microcontroller product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 * \asf_license_stop
 *
 */
/*
 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
 */
#include <clock.h>

#ifndef CONF_CLOCKS_H_INCLUDED
#  define CONF_CLOCKS_H_INCLUDED

/* System clock bus configuration */
#  define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT     false
#  define CONF_CLOCK_FLASH_WAIT_STATES            0
#  define CONF_CLOCK_CPU_DIVIDER                  SYSTEM_MAIN_CLOCK_DIV_1
#  define CONF_CLOCK_APBA_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
#  define CONF_CLOCK_APBB_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1
#  define CONF_CLOCK_APBC_DIVIDER                 SYSTEM_MAIN_CLOCK_DIV_1

/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
#  define CONF_CLOCK_OSC8M_PRESCALER              SYSTEM_OSC8M_DIV_1
#  define CONF_CLOCK_OSC8M_ON_DEMAND              true
#  define CONF_CLOCK_OSC8M_RUN_IN_STANDBY         false

/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
#  define CONF_CLOCK_XOSC_ENABLE                  false
#  define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL        SYSTEM_CLOCK_EXTERNAL_CRYSTAL
#  define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY      12000000UL
#  define CONF_CLOCK_XOSC_STARTUP_TIME            SYSTEM_XOSC_STARTUP_32768
#  define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL       true
#  define CONF_CLOCK_XOSC_ON_DEMAND               true
#  define CONF_CLOCK_XOSC_RUN_IN_STANDBY          false

/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
#  define CONF_CLOCK_XOSC32K_ENABLE               false
#  define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL     SYSTEM_CLOCK_EXTERNAL_CRYSTAL
#  define CONF_CLOCK_XOSC32K_STARTUP_TIME         SYSTEM_XOSC32K_STARTUP_65536
#  define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL  false
#  define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT    false
#  define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT  true
#  define CONF_CLOCK_XOSC32K_ON_DEMAND            true
#  define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY       false

/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
#  define CONF_CLOCK_OSC32K_ENABLE                false
#  define CONF_CLOCK_OSC32K_STARTUP_TIME          SYSTEM_OSC32K_STARTUP_130
#  define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT    true
#  define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT   true
#  define CONF_CLOCK_OSC32K_ON_DEMAND             true
#  define CONF_CLOCK_OSC32K_RUN_IN_STANDBY        false

/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
#  define CONF_CLOCK_DFLL_ENABLE                  false
#  define CONF_CLOCK_DFLL_LOOP_MODE               SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
#  define CONF_CLOCK_DFLL_ON_DEMAND               false

/* DFLL open loop mode configuration */
#  define CONF_CLOCK_DFLL_FINE_VALUE              (512)

/* DFLL closed loop mode configuration */
#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_1
#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)

/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
#  define CONF_CLOCK_DPLL_ENABLE                  false
#  define CONF_CLOCK_DPLL_ON_DEMAND               true
#  define CONF_CLOCK_DPLL_RUN_IN_STANDBY          false
#  define CONF_CLOCK_DPLL_LOCK_BYPASS             false
#  define CONF_CLOCK_DPLL_WAKE_UP_FAST            false
#  define CONF_CLOCK_DPLL_LOW_POWER_ENABLE        false

#  define CONF_CLOCK_DPLL_LOCK_TIME               SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
#  define CONF_CLOCK_DPLL_REFERENCE_CLOCK         SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
#  define CONF_CLOCK_DPLL_FILTER                  SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT

#  define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY     32768
#  define CONF_CLOCK_DPLL_REFERENCE_DIVIDER       1
#  define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY        48000000

/* DPLL GCLK reference configuration */
#  define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR  GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
#  define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR     GCLK_GENERATOR_1

/* Set this to true to configure the GCLK when running clocks_init. If set to
 * false, none of the GCLK generators will be configured in clocks_init(). */
#  define CONF_CLOCK_CONFIGURE_GCLK               true

/* Configure GCLK generator 0 (Main Clock) */
#  define CONF_CLOCK_GCLK_0_ENABLE                true
#  define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_0_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_0_PRESCALER             1
#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         false

/* Configure GCLK generator 1 */
#  define CONF_CLOCK_GCLK_1_ENABLE                false
#  define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_1_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_XOSC32K
#  define CONF_CLOCK_GCLK_1_PRESCALER             1
#  define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE         false

/* Configure GCLK generator 2 (RTC) */
#  define CONF_CLOCK_GCLK_2_ENABLE                false
#  define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_2_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
#  define CONF_CLOCK_GCLK_2_PRESCALER             32
#  define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE         false

/* Configure GCLK generator 3 */
#  define CONF_CLOCK_GCLK_3_ENABLE                false
#  define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_3_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_3_PRESCALER             1
#  define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE         false

/* Configure GCLK generator 4 */
#  define CONF_CLOCK_GCLK_4_ENABLE                false
#  define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_4_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_4_PRESCALER             1
#  define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE         false

/* Configure GCLK generator 5 */
#  define CONF_CLOCK_GCLK_5_ENABLE                false
#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_5_PRESCALER             1
#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false

/* Configure GCLK generator 6 */
#  define CONF_CLOCK_GCLK_6_ENABLE                false
#  define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_6_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_6_PRESCALER             1
#  define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE         false

/* Configure GCLK generator 7 */
#  define CONF_CLOCK_GCLK_7_ENABLE                false
#  define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_7_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_7_PRESCALER             1
#  define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE         false

/* Configure GCLK generator 8 */
#  define CONF_CLOCK_GCLK_8_ENABLE                false
#  define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_8_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_8_PRESCALER             1
#  define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE         false

#endif /* CONF_CLOCKS_H_INCLUDED */

 

Last Edited: Tue. Dec 19, 2017 - 06:33 PM
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Total votes: 0

I had a similar problem. It was solved by clearing the interrupt in the interrupt-handler.

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almost certainly nothing to do with the reported problem, but a general 'C' point:

winneymj13 wrote:

void configure_power_manager(void)
{
	system_apb_clock_clear_mask(
			SYSTEM_CLOCK_APB_APBA,
				(PM_APBAMASK_WDT \
				| PM_APBAMASK_PAC0 \
				| PM_APBAMASK_GCLK \
				| PM_APBAMASK_RTC \
				| PM_APBAMASK_PM \
				| PM_APBAMASK_SYSCTRL \
				/* These clocks should remain enabled on this bus
				| PM_APBAMASK_EIC \
				*/
				));	

etc

What are all those line continuation characters doing there?

 

The line continuation characters are only needed within a macro definition.

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Total votes: 1

Most times when you have high current in sleep it is from a GPIO pin not being configured correctly.  Go through each pin and write down what state (high, low, pulled high, pulled low) should be when sleeping.  Never leave an input pin floating with out a pull up or pull down as it might have low current during testing, but have high current later. 

 

I usually create a function that sets each pin (including SWD pins) to the correct state right before sleep.  Once this is done and I verify that the pins are all at the correct level, then I start debugging peripheral issues with high current in sleep. 

 

Trampas

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Hello,

I suggest you try running the whole program with the configuration in the while(true) loop and see if that solves the problem. If it works it means that the interrupt is changing a configuration you set. The goal is to verify that your initial configuration is what's running after the first standby.

 

Another thing, configure all your IO ports including analog to what the datasheet says about unused ports.

 

Application note AN42411 says :

"I/O Pin Configurations
For unused I/O pins, the default configuration should be used, as this disconnects the I/O pads from the
I/O pins, reducing the leakage current. With the default configuration for an I/O pin the bit corresponding
to the pin in the Data Direction (DIR) register, the Input Enable bit in the Pin Configuration y register
(PINCFGy.INEN), and the Pull Enable bit in the Pin Configuration y register (PINCFGy.PULLEN) are all
written to zero."

 

In my case that didn't get me the lowest consumption i configured all pins to OUTPUT and LOW with the following for loop:

  for (uint32_t ul = 0 ; ul < NUM_DIGITAL_PINS ; ul++ ) {
    pinMode( ul, OUTPUT ) ;
    digitalWrite(ul, LOW);
    }

Testing on Arduino.

 

Best of luck !

Last Edited: Fri. Apr 27, 2018 - 01:44 PM
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I'm experiencing the same issue. On a custom board with SAM D21G18A, running the Arduino Zero libraries. I have two interrupts configured, one on PB23 (ext int 7), which wakes up the microcontroller from sleep mode. Then I have another one on PA27 (ext int 15) configured in exactly the same way.

 

In sleep mode my board consumes between 10µA and 20µA. When the board is woken up by EXTERNAL_INT_7, the board momentarily consumes more power and goes back to sleep at the 10-20µA level.

 

But when I use EXTERNAL_INT_15 to wake up the board, the usage momentarily shoots up, and then comes down to ±350µA when the board goes back to sleep. This is strange as the two interrupts are configured exactly the same.

 

I have tried all the suggestions in this thread, setting all pins into known states that will prevent unnecessary current from flowing. So far I can't find a cause for the 350µA after the one interrupt fired.