SO8N package - pin 1?

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Krupski
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Posted by Krupski: Tue. Mar 10, 2020 - 11:23 PM
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Hi all,

 

I've got some 8 pin SOIC package chips in a tape. Pin 1 is not marked in any way on the chip!  There is no notch on the pin 1 end, no dot molded into the part, no asymmetry to the package, nothing to indicate where pin 1 is!

 

I wonder if there is a "standard" which defines WHERE pin 1 is in an SOIC tape? I Googled everywhere, found lots of SOIC tape info, but nothing that seems to indicate any pin location standard.

 

And, of course the datasheet for the chip does not indicate pin 1 either. The datasheet shows a line of some sort molded into the package, but there is no line on the actual chip.

 

Please see attached images.

 

(click thumbs for full size)

JPEG image

 

JPEG image

 

JPEG image

 

Any info will be appreciated!

This topic has a solution.

Gentlemen may prefer Blondes, but Real Men prefer Redheads!

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Learning and Information, General Electronics, solved
Last Edited: Wed. Mar 11, 2020 - 12:00 AM
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Kartman
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Posted by Kartman: Tue. Mar 10, 2020 - 11:27 PM
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There’s a clear bevel on the left hand side of the package.

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digitalDan
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Posted by digitalDan: Tue. Mar 10, 2020 - 11:47 PM
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Letting the smoke out since 1978

 

 

 

 

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Krupski
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Posted by Krupski: Wed. Mar 11, 2020 - 12:00 AM
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Kartman wrote:
There’s a clear bevel on the left hand side of the package.
digitalDan wrote:

 

WOW you're right!

 

I looked at the chip from the top and could see no difference. When I looked end-on, it was plainly visible! It's sort of like this (the vertical "pipe" symbol representing the less sloped side):

 

 ______

/      |

-------

 

(how did I not see it before?)

 

Thanks!

 

Gentlemen may prefer Blondes, but Real Men prefer Redheads!

Last Edited: Wed. Mar 11, 2020 - 12:01 AM
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valusoft
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Posted by valusoft: Wed. Mar 11, 2020 - 04:03 AM
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And clearly documented on the drawing.

 

Ross McKenzie, Melbourne Australia

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avrcandies
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Posted by avrcandies: Wed. Mar 11, 2020 - 04:26 AM
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As they say, the bevel is in the details.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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mnehpets
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Posted by mnehpets: Wed. Mar 11, 2020 - 06:26 AM
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avrcandies wrote:

As they say, the bevel is in the details.

 

10/10!

 

- S

 

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barnacle
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Posted by barnacle: Wed. Mar 11, 2020 - 01:46 PM
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Also, the chip datasheet often includes a spec for the packaging (strip, boxes etc, not the chip itself) which should include things like where pin one is, so it can be fed into pnp machines.

 

Neil

Neil Barnes
www.nailed-barnacle.co.uk

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Bronze Markawneil
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Posted by awneil: Wed. Mar 11, 2020 - 02:03 PM (Reply to #8)
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barnacle wrote:
Also, the chip datasheet often includes a spec for the packaging:

No doubt that's where the OP's diagram came from ?

 

which should include things like where pin one is

and, as Ross pointed out, it does:

 

 

 

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Gold Markclawson
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Posted by clawson: Wed. Mar 11, 2020 - 02:11 PM
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I'm more "old school" and would simply have gone on the principle that chips tend to be:

 

This went a bit Pete Tong when you posted the photo the wrong way up:

 

 

if you turned it the right way up so the ST logo was clearly visible then it seems to conform to my simplistic, old school pattern too....

 

 

(this cunning plan goes to hell in a handcart on the occasion that they load the chips into the silk screening machine the "wrong way up" ! ;-)

 

Last Edited: Wed. Mar 11, 2020 - 02:13 PM
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barnacle
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Posted by barnacle: Thu. Mar 12, 2020 - 12:26 PM
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@AWNeil - yes, that's the *package* drawings; I had in mind the *packing* drawings... which I've certainly seen on datasheets before but a random ST processor datasheet I just looked at didn't have...

 

Ah! It's in the technical notes for ST: TN1205 https://www.st.com/resource/en/t... looks like what you need.

 

Neil

Neil Barnes
www.nailed-barnacle.co.uk

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