megaAVR-0 TWI IO config?

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Presume this also applies to tinyAVR-0/1 ... Two questions:

 

1) It appears that only TWI0 has alternate IO pins. Is this interpretation correct? In documentation on PORTMUX (megaAVR-0-series Family Data Sheet), only TWI0 seems to have control bits. <ERROR>I had assumed that 4808/9, etc, had more than one TWI interface. Just discovered that there is ONLY one,  So, the question is nonsense. Sorry. </ERROR>

 

2) What are the appropriate settings for the SDA and SCL pins? Do you set both as output? Or does it have to be switched between TWI read and write operations? Is there an outut pin mode that really behaves open-drain? In particular, the Family Data Sheet says:

 

Peripherals such as USARTs and timers may be connected to I/O pins. Such peripherals will usually have a primary and optionally also alternate I/O pin connection, selectable by PORTMUX. By configuring and enabling such peripherals, the general-purpose I/O pin behavior normally controlled by PORT will be overridden by the peripheral in a peripheral-dependent way. Some peripherals may not override all of the PORT registers, leaving the PORT module to control some aspects of the I/O pin operation. Refer to the description of each peripheral for information on the peripheral override. Any pin in a PORT which is not overridden by a peripheral will continue to operate as a general- purpose I/O pin.

There does not seem to be a statement in the TWI chapter about this. 

 

Thanks for your help!

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Feb 3, 2020 - 07:57 PM
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Have you looked at the TWI code posted in the app note thread?  It has code for alternate port settings.

Jim

 

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It shows sample code that selects standard or alternate port for TWI0. There does not seem to be any register control for alternate port on other TWI interfaces, thus the question. <EDIT>See change in Msg #1</EDIT>

 

In same sample code or documentation, there does not seem to be much about direction management, or open-drain function. Thus, the second question. It would be nice if all this happens automagically, but lacking information, it is hard to know.

 

Jim

 

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Mon. Feb 3, 2020 - 07:58 PM
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There is only one twi (TWI0). You have 2 pairs of pins to choose from for master/slave mode SCL(MS),SCA(MS), which PORTMUX will select. There is also the option to use DUAL mode where the slave gets its own set of pins but only one option- SCL(S),SCA(S).

 

I would presume the twi uses the dir and out override for the sca/scl pins which means you have nothing to do (except enable the internal pullup if wanted, even if not strong enough). When dir is set to input, the pullup takes effect which gives the open-drain appearance. They don't mention anything in the twi chapter about the port settings, so you can assume there is nothing to do except select via portmux.

 

edit-

they most likely take over input disable override also, otherwise they would make sure to tell you that input cannot be disabled.

Last Edited: Mon. Feb 3, 2020 - 08:03 PM
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Thanks

 

Jim

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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I'm afraid that code is the best we have at this point until MC finally comes around to making an app note:

What does atmel start give you if anything.

Jim

 

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I need to bite the bullet and do Start. My task for the next day or two or whatever.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Let know if you survive! wink

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I think they missed talking about the 'invert enable' in the ports, as that would have to be off (and appears to have no override signal). That seems to be the only thing you could do to mess up the scx pins. It would be nice if they would mention the port setup a little more in twi chapter, and if the invert enable has to be off, just say so.

 

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Missed that about the invert feature. That could be a killer if accidentally enabled.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Jim
This is in reference to the M4809 right?

I believe it's in the TWI section under register description where you pick the primary or alternate pins. And you set the port direction to output for the chosen pins

Not at my PC...gimme a few minutes
Other Jim

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Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

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Found it!  Its in teh MegaAVR-0 series datasheet under PORTMUX

 

Here You go:

 

 

Other Jim

 

 

 

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

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I got that, OK. Question 2 really breaks down to "what sets the pin configuration" for TWI. This question arises from the spec sheet quote in Msg #1 which I requote:

 

Peripherals such as USARTs and timers may be connected to I/O pins. Such peripherals will usually have a primary and optionally also alternate I/O pin connection, selectable by PORTMUX. By configuring and enabling such peripherals, the general-purpose I/O pin behavior normally controlled by PORT will be overridden by the peripheral in a peripheral-dependent way. Some peripherals may not override all of the PORT registers, leaving the PORT module to control some aspects of the I/O pin operation. Refer to the description of each peripheral for information on the peripheral override. Any pin in a PORT which is not overridden by a peripheral will continue to operate as a general- purpose I/O pin.

So, does TWI over-ride the PORT config? The peripheral description does not contain anything that I could find. If there is no over-ride, then what do you set the PORT config to? That is also not specified.

 

Thanks

Jim 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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On the 48 pin 4808/9 you can have combined master+slave on pins 46+47 or on pins 12+13 or you can have just the master on one of those pairs and independent slave on pins 36+37.

(Or just the master of course.)

 

 

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ka7ehk wrote:
So, does TWI over-ride the PORT config?

 

Yes and no.  You must configure teh port pins as outputs.  It is not done automatically.

 

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

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So, even though a normal output is hard pull up, and hard pull down, the TWI pins behave as open-drain outputs without any additional configuration?

 

Thanks

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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You are making it more complicated than it is. The following is with an attiny817 xplained board, but a 4809 is the same idea. The twi0 peripheral is in control of everything except the external/internal pullups (it also seems to use the analog path on input, or is controlling the inven in some way that does not show up when debugging, as inven has no effect). Choose which set of pins you want to use, and if using the default set you don''t even have to touch portmux.

 

#include <avr/io.h>
#define F_CPU 3333333ul
#include <util/delay.h>

//tiny817 Xplained
//default 3.33MHz
//twi alternate pins, I already have default pins used for something else
//PA1 - SDA
//PA2 - SCL

int main(){

    PORTMUX.CTRLB = 1<<4; //TWI0 alt pin
    PORTA.PIN1CTRL = 1<<3; //pullup on, this will do for testing
    PORTA.PIN2CTRL = 1<<3; //pullup on, this will do for testing

 

    TWI0.MBAUD = 10; //100kHz -> BAUD = F_CPU * 4.7us - 5
    TWI0.MCTRLA = 1; //enable
    TWI0.MSTATUS = 1; //set to idle

 

    for(;;){ //just send a start so can see on logic analyzer
        TWI0.MADDR = 0x01; //address 0, read
        _delay_us(100);
        TWI0.MADDR = 0x00; //address 0, write
        _delay_ms(100);
    }
}

 

 

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THANKS!  Come from the tradition of "measure several times, then cut once".

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net