PWM Duty Cycle

Go To Last Post
12 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

 

I had a question in regards to the PWM duty cycle in inverting mode and non inverting mode, it specifies in the mazidi avr book that the non inverting mode cant reach 0% duty cycle and the inverting mode cant reach a 100% duty cycle, I can see it is mathematically obvious from the derived equation for the duty cycle, but I wanted to understand more in depth why the duty cycle has OCR0+1 in non inverting and in the inverting its is 255-OCR0 not 256?

Attachment(s): 

This topic has a solution.

Sherif Nassar

Last Edited: Wed. Jan 29, 2020 - 04:34 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0


It's a lot easier if you put the picture in the post - where we can see it:

 

 

For instructions to do that, see Tip #1 in my signature (below; may not be visible on mobile)

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

done

Sherif Nassar

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

the non inverting mode cant reach 0% duty cycle and the inverting mode cant reach a 100% duty cycle

This is true and has been discussed quite often 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

well i've searched multiple times before posting this, most discussions just end with someone posting this equation and says it is obvious from the equation..which is..I am not asking about just putting values for OCR in the equation I am trying to understand how it is derived, I know it is true, but why is it? why the non inverting has a +1 in the numerator and not only OCR0 ? and why the inverting has the 255 and can reach the 100%?

Sherif Nassar

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

sherifb96 wrote:
... I wanted to understand more in depth why the duty cycle has OCR0+1 in non inverting and in the inverting its is 255-OCR0 not 256?

Because the 8-bit output comparison registers only range from 0-255 (256 possibilities), whereas the duty cycle you could generate with an 8-bit count cycle is 0/256 through 256/256 (257 possibilities). A comparison register is one possibility short, so the designer(s) dropped 1 of the 257 possible duty cycles: 0/256 in non-inverting and 256/256 in inverting.

 

I find  too much ambiguity and contradiction in the datasheets to decide whether these particular dropped values were chosen or just "happened". I lean toward "happened".

- John

Last Edited: Tue. Jan 28, 2020 - 07:49 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thank you John for responding, well I seem to understand the concept of what you are saying and I understand the part of the 8 bit register ranges from 0-255 giving 256 possibilities, but how can an 8bit count for the duty cycle generate 257 possibility this is just what I dont yet understand? I see this must be the key to my misunderstanding and I would like to thank you for clarifying.

Sherif Nassar

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

You got it: 8-bits can not specify 257 possibilities. The conceptual and operational issue is the PWM units disadvantage one of the 257 possibilities. To get it requires hacks that often work.

- John

Last Edited: Tue. Jan 28, 2020 - 08:17 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I mean why the duty cycle has 257 possibilities? if the counting ranges from 0-255(256 possibilities) shoudln't the 255 suffice for a 100% duty cycle and 0 for a 0% duty cycle? why is there a 257 possibility? 

Sherif Nassar

This reply has been marked as the solution. 
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

It is because fully off (in non-inverting mode) or fully on (in inverting mode) is a 257th possibility that the compare units (in full, 8-bit mode) can not specify. Consider non-inverting mode:

  • 0 specifies 1/256 on (nearly off)
  • 1 specifies 2/256 on
  • 2 specifies 3/256 on
  • ...
  • 253 specifies 254/256 on
  • 254 specifies 255/256 on
  • 255 specifies 256/256 on (fully on)

That is it. The hardware has used up all 256 possible compare register values to specify 256 duty cycles. But you might want a 257th duty cycle

  • ... 0/256 on (fully off)

The issue you will probably next encounter is: how are you going to get that? Not with the compare register: its 256 possible values are already assigned.

 

- John

Last Edited: Tue. Jan 28, 2020 - 08:50 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

It's the simplistic method they chose that gives you the scenario...essentially:

tick: turn on the output

tick: is it time to turn off?

tick: is it time to turn off?

tick: is it time to turn off? Yes==>turn off

 

So it will always be on for at least one tick.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ahaa, understood, thank you!

Sherif Nassar