Getting started with ATTiny1614

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The ATTiny1614 event system and CCL looks really awesome!    

 

But, I'm struggling a bit to on understanding how to configure it versus the enums I see in iotn1614.h

 

First anomaly I saw was that iotn1614.h is NOT referenced in avr/io.h -- even after  I updated to the latest Studio 7 and installed everything under Device Pack Manager.  I mention that, since maybe the header file is not really "ready for prime time".  

 

But,  I hacked io.h to add an include iotn1614.h:

#elif defined (__AVR_ATtiny1614__)
#  include <avr/iotn1614.h>

There are the usual slight discrepancies between how the datasheet spells registers versus what's in the header file.  But, I'm really confused by some of the enums, which makes me wonder if I really understand how things work.  For example:

 

/* EVSYS - Event System */
/* EVSYS.ASYNCCH0  bit masks and bit positions */
#define EVSYS_ASYNCCH0_gm  0xFF  /* Asynchronous Channel 0 Generator Selection group mask. */
#define EVSYS_ASYNCCH0_gp  0  /* Asynchronous Channel 0 Generator Selection group position. */
#define EVSYS_ASYNCCH00_bm  (1<<0)  /* Asynchronous Channel 0 Generator Selection bit 0 mask. */
#define EVSYS_ASYNCCH00_bp  0  /* Asynchronous Channel 0 Generator Selection bit 0 position. */
#define EVSYS_ASYNCCH01_bm  (1<<1)  /* Asynchronous Channel 0 Generator Selection bit 1 mask. */
#define EVSYS_ASYNCCH01_bp  1  /* Asynchronous Channel 0 Generator Selection bit 1 position. */
#define EVSYS_ASYNCCH02_bm  (1<<2)  /* Asynchronous Channel 0 Generator Selection bit 2 mask. */
#define EVSYS_ASYNCCH02_bp  2  /* Asynchronous Channel 0 Generator Selection bit 2 position. */
#define EVSYS_ASYNCCH03_bm  (1<<3)  /* Asynchronous Channel 0 Generator Selection bit 3 mask. */
#define EVSYS_ASYNCCH03_bp  3  /* Asynchronous Channel 0 Generator Selection bit 3 position. */
#define EVSYS_ASYNCCH04_bm  (1<<4)  /* Asynchronous Channel 0 Generator Selection bit 4 mask. */
#define EVSYS_ASYNCCH04_bp  4  /* Asynchronous Channel 0 Generator Selection bit 4 position. */
#define EVSYS_ASYNCCH05_bm  (1<<5)  /* Asynchronous Channel 0 Generator Selection bit 5 mask. */
#define EVSYS_ASYNCCH05_bp  5  /* Asynchronous Channel 0 Generator Selection bit 5 position. */
#define EVSYS_ASYNCCH06_bm  (1<<6)  /* Asynchronous Channel 0 Generator Selection bit 6 mask. */
#define EVSYS_ASYNCCH06_bp  6  /* Asynchronous Channel 0 Generator Selection bit 6 position. */
#define EVSYS_ASYNCCH07_bm  (1<<7)  /* Asynchronous Channel 0 Generator Selection bit 7 mask. */
#define EVSYS_ASYNCCH07_bp  7  /* Asynchronous Channel 0 Generator Selection bit 7 position. */

As I read the attiny1614 spec, there are 13 peripherals (n= 0 to n=12) that can have inputs from the ASYNC generators.  Each of those event "consumers" has a dedicated register that defines which event channel that peripheral should use as an input (the values SYNCCH0, SYNCCH1, ASSYNCCH0, etc):

 

 

So, for example, say I want TCB0 to have its input from an event channel 0.  I assume I do this:

 

EVSYS.ASYNCUSER0 = EVSYS_ASYNCUSER0_ASYNCCH0_gc;

Since this is in iotn1614.h:

typedef enum EVSYS_ASYNCUSER0_enum
{
    EVSYS_ASYNCUSER0_OFF_gc = (0x00<<0),  /* Off */
    EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0),  /* Synchronous Event Channel 0 */
    EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0),  /* Synchronous Event Channel 1 */
    EVSYS_ASYNCUSER0_ASYNCCH0_gc = (0x03<<0),  /* Asynchronous Event Channel 0 */
    EVSYS_ASYNCUSER0_ASYNCCH1_gc = (0x04<<0),  /* Asynchronous Event Channel 1 */
    EVSYS_ASYNCUSER0_ASYNCCH2_gc = (0x05<<0),  /* Asynchronous Event Channel 2 */
    EVSYS_ASYNCUSER0_ASYNCCH3_gc = (0x06<<0),  /* Asynchronous Event Channel 3 */
} EVSYS_ASYNCUSER0_t;

I think the command is setting up user0 (Timer B0) to use Asynchrouse event channel 0.

 

But, I also see this in iotn1614.h:

 

/* EVSYS.ASYNCUSER0  bit masks and bit positions */
#define EVSYS_ASYNCUSER0_gm  0xFF  /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */
#define EVSYS_ASYNCUSER0_gp  0  /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */
#define EVSYS_ASYNCUSER00_bm  (1<<0)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */
#define EVSYS_ASYNCUSER00_bp  0  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */
#define EVSYS_ASYNCUSER01_bm  (1<<1)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */
#define EVSYS_ASYNCUSER01_bp  1  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */
#define EVSYS_ASYNCUSER02_bm  (1<<2)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */
#define EVSYS_ASYNCUSER02_bp  2  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */
#define EVSYS_ASYNCUSER03_bm  (1<<3)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */
#define EVSYS_ASYNCUSER03_bp  3  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */
#define EVSYS_ASYNCUSER04_bm  (1<<4)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */
#define EVSYS_ASYNCUSER04_bp  4  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */
#define EVSYS_ASYNCUSER05_bm  (1<<5)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */
#define EVSYS_ASYNCUSER05_bp  5  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */
#define EVSYS_ASYNCUSER06_bm  (1<<6)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */
#define EVSYS_ASYNCUSER06_bp  6  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */
#define EVSYS_ASYNCUSER07_bm  (1<<7)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */
#define EVSYS_ASYNCUSER07_bp  7  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */

I don't see how those those bit position and bitmasks would be used.  The first enum (EVSYS_ASYNCUSER0_enum) has the only valid values indicated in the spec.

 

So, either this is just nonsense in the header file, or I'm missing something (probably the latter).

 

Also, the enum CCL_INS0_enum:

/* LUT Input 0 Source Selection select */
typedef enum CCL_INSEL0_enum
{
    CCL_INSEL0_MASK_gc = (0x00<<0),  /* Masked input */
    CCL_INSEL0_FEEDBACK_gc = (0x01<<0),  /* Feedback input source */
    CCL_INSEL0_LINK_gc = (0x02<<0),  /* Linked LUT input source */
    CCL_INSEL0_EVENT0_gc = (0x03<<0),  /* Event input source 0 */
    CCL_INSEL0_EVENT1_gc = (0x04<<0),  /* Event input source 1 */
    CCL_INSEL0_IO_gc = (0x05<<0),  /* IO pin LUTn-IN0 input source */
    CCL_INSEL0_AC0_gc = (0x06<<0),  /* AC0 OUT input source */
    CCL_INSEL0_TCB0_gc = (0x07<<0),  /* TCB0 WO input source */
    CCL_INSEL0_TCA0_gc = (0x08<<0),  /* TCA0 WO0 input source */
    CCL_INSEL0_TCD0_gc = (0x09<<0),  /* TCD0 WOA input source */
    CCL_INSEL0_USART0_gc = (0x0A<<0),  /* USART0 XCK input source */
    CCL_INSEL0_SPI0_gc = (0x0B<<0),  /* SPI0 SCK source */
} CCL_INSEL0_t;

The enum doesn't include all the values for AC1, TCB1, and AC2.  I'm assuming the spec is correct and the enum is outdated.

 

 

 

 

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davethomaspilot wrote:
First anomaly I saw was that iotn1614.h is NOT referenced in avr/io.h

 

It just seems so. Actually they use a trick, it's included by these lines

 

#  define __AVR_DEVICE_HEADER__ <avr/__header1__(io,__AVR_DEV_LIB_NAME__).h>
#  include __AVR_DEVICE_HEADER__

 

The __AVR_DEV_LIB_NAME__ is defined in the device specs to point to the right header.

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Ah, thanks for that.

 

Still, I don't understand the EVSYS.ASYNCUSER bit masks and bit positions.  

 

I just want to make sure I understand how to configure the ASYNCUSER.  One 8 bit register for each peripheral than can consume an ASYNC event.  The contents of the register define one of 6 event channels that can be used (or it can be "Off")

 

I though the other "issues" might be a hint about the validity of the header file.

 

 

 

 


 
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What is going on with you?
I can include iotn1614.h and build the code successfully.

 

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That part of the post was already answered by El Tangas. Thanks for that.

 

But,   It's really not the main point.

 

 

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I think you need to read this:

 

http://ww1.microchip.com/downloa...

 

to understand what all the _bp, _bm, _gc suffixes are all about.

 

Bottom line _gc's (bit groups) are just a second ("higher level" ?) way to make use of invidual bits (_bp , _bm).

 

So don't be confused when you see both:

#define EVSYS_ASYNCUSER01_bm  (1<<1)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */
#define EVSYS_ASYNCUSER01_bp  1  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */
#define EVSYS_ASYNCUSER02_bm  (1<<2)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */
#define EVSYS_ASYNCUSER02_bp  2  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */

and

    EVSYS_ASYNCUSER0_SYNCCH0_gc = (0x01<<0),  /* Synchronous Event Channel 0 */
    EVSYS_ASYNCUSER0_SYNCCH1_gc = (0x02<<0),  /* Synchronous Event Channel 1 */

Sure, on this particular occasion it's perhaps confusing that the _gc's are the same (bit patterns) as the _bm's but the preference would be to use the _gc's usually when they are available.

 

Perhaps a clearer example of this is (picked almost totally at random from the .h) the analog comparator. It has two bits (1 and 2):

#define AC_HYSMODE_gm  0x06  /* Hysteresis Mode group mask. */
#define AC_HYSMODE_gp  1  /* Hysteresis Mode group position. */
#define AC_HYSMODE0_bm  (1<<1)  /* Hysteresis Mode bit 0 mask. */
#define AC_HYSMODE0_bp  1  /* Hysteresis Mode bit 0 position. */
#define AC_HYSMODE1_bm  (1<<2)  /* Hysteresis Mode bit 1 mask. */
#define AC_HYSMODE1_bp  2  /* Hysteresis Mode bit 1 position. */

but the use of the two bits is usually as a 2 bit pattern in a group of 2:

typedef enum AC_HYSMODE_enum
{
    AC_HYSMODE_OFF_gc = (0x00<<1),  /* No hysteresis */
    AC_HYSMODE_10mV_gc = (0x01<<1),  /* 10mV hysteresis */
    AC_HYSMODE_25mV_gc = (0x02<<1),  /* 25mV hysteresis */
    AC_HYSMODE_50mV_gc = (0x03<<1),  /* 50mV hysteresis */
} AC_HYSMODE_t;

So say you wanted "50mV" operation. You could:

AC0.CTRLA = AC_HYSMODE0_bm | AC_HYSMODE1_bm;

but the only way the maintainer (also you in 18 months) would know this selects 50mV mode would be if you write:

AC0.CTRLA = AC_HYSMODE0_bm | AC_HYSMODE1_bm; // select 50mV mode

but if you used the "higher level" _gc's the line would be self documenting as:

AC0.CTRLA = AC_HYSMODE_50mV_gc;

 

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I'm assuming the spec is correct and the enum is outdated.

Not sure I'd make that assumption. On the whole the ioXXX.h files are autogenerated from the .atdf part description files (XML) so they should have everything the part contains. If it's not in the .atdf (and hence .h) then the chances are the part does not have it whatever the datasheet might suggest (never known for their accuracy!)

 

EDIT: yup this is what I see in the .ATDF for 1614:

 

 

so this does not include the 0x0C, 0x0D, 0x0E values for AC1, TCB1, AC2 that the datasheet seems to think are also available.

 

PS caveat - I don't know if I have the latest pack (using 1.3.229) - it's vaguely possible this may have been changed/corrected in a later issue.

Last Edited: Tue. Jan 14, 2020 - 09:56 AM
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Not sure I'd make that assumption. On the whole the ioXXX.h files are autogenerated from the .atdf part description files (XML) so they should have everything the part contains

That has saved me several times...I assumed those files are correct & ignored some of the cut & paste datasheet errors & my troubles became minor tribbles.

 

The bit groups are generally handy in reading/understanding what the setups are doing.  Unfortunately (for some annoying reason) many times chip bits get separated (2 of 3 bits in reg  CTRLTMR0CAT & the 3rd bit over in CTRLTMR0DOG)  

I seem to remember WGM bits being like that. 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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clawson wrote:
whatever the datasheet might suggest (never known for their accuracy!)

In Atmel days, they certainly had the capability to generate the datasheet register descriptions from the chip design XML ...

 

EDIT

 

To expand a little, that would be the register names & addresses, bit names, and bit layouts within the registers.

 

I think the words describing them were still manual.

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Last Edited: Tue. Jan 14, 2020 - 11:02 AM
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look at this in the header file-

 

/* C Language Only */
#if !defined (__ASSEMBLER__)

... //all C things in here

#endif /* !defined (__ASSEMBLER__) */

 

//now stuff that can be used in assembler also,

//which are all defines and duplicate much of the above

//because well, assembler is not C-

...

 

So you have one header file that can be used for both C and assembly (if using pre-processor anyway). If using C, use the C section as much as possible- not that the other doesn't also work but so you have a consistent way of doing things. Its easy to get lazy and use defines when there was a struct/enum to do the job, but you end up with a mixed use of both and the reader (you) will never know why one or the other is being used. 

 

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 Thanks for the replies!

 

From Clawson:

so this does not include the 0x0C, 0x0D, 0x0E values for AC1, TCB1, AC2 that the datasheet seems to think are also available.

 

Ok, we agree on that then.  The header file is inconsistent with the spec.  I'm assuming the spec is correct, but hopefully will find out soon.  M

 

Also from Clawson:

 

I think you need to read this:

 

http://ww1.microchip.com/downloa...

 

Thanks for the reference, Clawson.  It's good to know the naming conventions. 

 

But, it's not that I don't understand how to use the enums to address bits in eight bit registers--I do that extensively and specifically with the attiny1614's analog comparators, CCL, and timers.   

 

The #define set that I posted provides symbolic constants to individually address each bit in and 8 bit register.  But if my understanding of how to configure the EVTSYS is correct (and this is the big IF and the purpose of my question!) most of the bits in the registers have no purpose and there would never be a reason to address them individually.

 

Please look closely at the spec  for the spec for ASYNCUSER[7:0].  It's in the original post.  I think the spec the only valid values for those 8 registers is 0x0,0x1,0x2,0x3,0x4,0x5, and 0x6.  The existence of all those records makes me question my understanding of EVTSYS configuration.

 

And similar #defines are in the file for not only the ASYNCUSER[7:0] registers.  The same "macros" are repeated many times, renamed for each individual register in the register sets: 

 

 

/* EVSYS - Event System */
/* EVSYS.ASYNCCH0  bit masks and bit positions */
#define EVSYS_ASYNCCH0_gm  0xFF  /* Asynchronous Channel 0 Generator Selection group mask. */
#define EVSYS_ASYNCCH0_gp  0  /* Asynchronous Channel 0 Generator Selection group position. */
#define EVSYS_ASYNCCH00_bm  (1<<0)  /* Asynchronous Channel 0 Generator Selection bit 0 mask. */
#define EVSYS_ASYNCCH00_bp  0  /* Asynchronous Channel 0 Generator Selection bit 0 position. */
#define EVSYS_ASYNCCH01_bm  (1<<1)  /* Asynchronous Channel 0 Generator Selection bit 1 mask. */
#define EVSYS_ASYNCCH01_bp  1  /* Asynchronous Channel 0 Generator Selection bit 1 position. */
#define EVSYS_ASYNCCH02_bm  (1<<2)  /* Asynchronous Channel 0 Generator Selection bit 2 mask. */
#define EVSYS_ASYNCCH02_bp  2  /* Asynchronous Channel 0 Generator Selection bit 2 position. */
#define EVSYS_ASYNCCH03_bm  (1<<3)  /* Asynchronous Channel 0 Generator Selection bit 3 mask. */
#define EVSYS_ASYNCCH03_bp  3  /* Asynchronous Channel 0 Generator Selection bit 3 position. */
#define EVSYS_ASYNCCH04_bm  (1<<4)  /* Asynchronous Channel 0 Generator Selection bit 4 mask. */
#define EVSYS_ASYNCCH04_bp  4  /* Asynchronous Channel 0 Generator Selection bit 4 position. */
#define EVSYS_ASYNCCH05_bm  (1<<5)  /* Asynchronous Channel 0 Generator Selection bit 5 mask. */
#define EVSYS_ASYNCCH05_bp  5  /* Asynchronous Channel 0 Generator Selection bit 5 position. */
#define EVSYS_ASYNCCH06_bm  (1<<6)  /* Asynchronous Channel 0 Generator Selection bit 6 mask. */
#define EVSYS_ASYNCCH06_bp  6  /* Asynchronous Channel 0 Generator Selection bit 6 position. */
#define EVSYS_ASYNCCH07_bm  (1<<7)  /* Asynchronous Channel 0 Generator Selection bit 7 mask. */
#define EVSYS_ASYNCCH07_bp  7  /* Asynchronous Channel 0 Generator Selection bit 7 position. */

/* EVSYS.ASYNCCH1  bit masks and bit positions */
#define EVSYS_ASYNCCH1_gm  0xFF  /* Asynchronous Channel 1 Generator Selection group mask. */
#define EVSYS_ASYNCCH1_gp  0  /* Asynchronous Channel 1 Generator Selection group position. */
#define EVSYS_ASYNCCH10_bm  (1<<0)  /* Asynchronous Channel 1 Generator Selection bit 0 mask. */
#define EVSYS_ASYNCCH10_bp  0  /* Asynchronous Channel 1 Generator Selection bit 0 position. */
#define EVSYS_ASYNCCH11_bm  (1<<1)  /* Asynchronous Channel 1 Generator Selection bit 1 mask. */
#define EVSYS_ASYNCCH11_bp  1  /* Asynchronous Channel 1 Generator Selection bit 1 position. */
#define EVSYS_ASYNCCH12_bm  (1<<2)  /* Asynchronous Channel 1 Generator Selection bit 2 mask. */
#define EVSYS_ASYNCCH12_bp  2  /* Asynchronous Channel 1 Generator Selection bit 2 position. */
#define EVSYS_ASYNCCH13_bm  (1<<3)  /* Asynchronous Channel 1 Generator Selection bit 3 mask. */
#define EVSYS_ASYNCCH13_bp  3  /* Asynchronous Channel 1 Generator Selection bit 3 position. */
#define EVSYS_ASYNCCH14_bm  (1<<4)  /* Asynchronous Channel 1 Generator Selection bit 4 mask. */
#define EVSYS_ASYNCCH14_bp  4  /* Asynchronous Channel 1 Generator Selection bit 4 position. */
#define EVSYS_ASYNCCH15_bm  (1<<5)  /* Asynchronous Channel 1 Generator Selection bit 5 mask. */
#define EVSYS_ASYNCCH15_bp  5  /* Asynchronous Channel 1 Generator Selection bit 5 position. */
#define EVSYS_ASYNCCH16_bm  (1<<6)  /* Asynchronous Channel 1 Generator Selection bit 6 mask. */
#define EVSYS_ASYNCCH16_bp  6  /* Asynchronous Channel 1 Generator Selection bit 6 position. */
#define EVSYS_ASYNCCH17_bm  (1<<7)  /* Asynchronous Channel 1 Generator Selection bit 7 mask. */
#define EVSYS_ASYNCCH17_bp  7  /* Asynchronous Channel 1 Generator Selection bit 7 position. */

/* EVSYS.ASYNCCH2  bit masks and bit positions */
#define EVSYS_ASYNCCH2_gm  0xFF  /* Asynchronous Channel 2 Generator Selection group mask. */
#define EVSYS_ASYNCCH2_gp  0  /* Asynchronous Channel 2 Generator Selection group position. */
#define EVSYS_ASYNCCH20_bm  (1<<0)  /* Asynchronous Channel 2 Generator Selection bit 0 mask. */
#define EVSYS_ASYNCCH20_bp  0  /* Asynchronous Channel 2 Generator Selection bit 0 position. */
#define EVSYS_ASYNCCH21_bm  (1<<1)  /* Asynchronous Channel 2 Generator Selection bit 1 mask. */
#define EVSYS_ASYNCCH21_bp  1  /* Asynchronous Channel 2 Generator Selection bit 1 position. */
#define EVSYS_ASYNCCH22_bm  (1<<2)  /* Asynchronous Channel 2 Generator Selection bit 2 mask. */
#define EVSYS_ASYNCCH22_bp  2  /* Asynchronous Channel 2 Generator Selection bit 2 position. */
#define EVSYS_ASYNCCH23_bm  (1<<3)  /* Asynchronous Channel 2 Generator Selection bit 3 mask. */
#define EVSYS_ASYNCCH23_bp  3  /* Asynchronous Channel 2 Generator Selection bit 3 position. */
#define EVSYS_ASYNCCH24_bm  (1<<4)  /* Asynchronous Channel 2 Generator Selection bit 4 mask. */
#define EVSYS_ASYNCCH24_bp  4  /* Asynchronous Channel 2 Generator Selection bit 4 position. */
#define EVSYS_ASYNCCH25_bm  (1<<5)  /* Asynchronous Channel 2 Generator Selection bit 5 mask. */
#define EVSYS_ASYNCCH25_bp  5  /* Asynchronous Channel 2 Generator Selection bit 5 position. */
#define EVSYS_ASYNCCH26_bm  (1<<6)  /* Asynchronous Channel 2 Generator Selection bit 6 mask. */
#define EVSYS_ASYNCCH26_bp  6  /* Asynchronous Channel 2 Generator Selection bit 6 position. */
#define EVSYS_ASYNCCH27_bm  (1<<7)  /* Asynchronous Channel 2 Generator Selection bit 7 mask. */
#define EVSYS_ASYNCCH27_bp  7  /* Asynchronous Channel 2 Generator Selection bit 7 position. */

/* EVSYS.ASYNCCH3  bit masks and bit positions */
#define EVSYS_ASYNCCH3_gm  0xFF  /* Asynchronous Channel 3 Generator Selection group mask. */
#define EVSYS_ASYNCCH3_gp  0  /* Asynchronous Channel 3 Generator Selection group position. */
#define EVSYS_ASYNCCH30_bm  (1<<0)  /* Asynchronous Channel 3 Generator Selection bit 0 mask. */
#define EVSYS_ASYNCCH30_bp  0  /* Asynchronous Channel 3 Generator Selection bit 0 position. */
#define EVSYS_ASYNCCH31_bm  (1<<1)  /* Asynchronous Channel 3 Generator Selection bit 1 mask. */
#define EVSYS_ASYNCCH31_bp  1  /* Asynchronous Channel 3 Generator Selection bit 1 position. */
#define EVSYS_ASYNCCH32_bm  (1<<2)  /* Asynchronous Channel 3 Generator Selection bit 2 mask. */
#define EVSYS_ASYNCCH32_bp  2  /* Asynchronous Channel 3 Generator Selection bit 2 position. */
#define EVSYS_ASYNCCH33_bm  (1<<3)  /* Asynchronous Channel 3 Generator Selection bit 3 mask. */
#define EVSYS_ASYNCCH33_bp  3  /* Asynchronous Channel 3 Generator Selection bit 3 position. */
#define EVSYS_ASYNCCH34_bm  (1<<4)  /* Asynchronous Channel 3 Generator Selection bit 4 mask. */
#define EVSYS_ASYNCCH34_bp  4  /* Asynchronous Channel 3 Generator Selection bit 4 position. */
#define EVSYS_ASYNCCH35_bm  (1<<5)  /* Asynchronous Channel 3 Generator Selection bit 5 mask. */
#define EVSYS_ASYNCCH35_bp  5  /* Asynchronous Channel 3 Generator Selection bit 5 position. */
#define EVSYS_ASYNCCH36_bm  (1<<6)  /* Asynchronous Channel 3 Generator Selection bit 6 mask. */
#define EVSYS_ASYNCCH36_bp  6  /* Asynchronous Channel 3 Generator Selection bit 6 position. */
#define EVSYS_ASYNCCH37_bm  (1<<7)  /* Asynchronous Channel 3 Generator Selection bit 7 mask. */
#define EVSYS_ASYNCCH37_bp  7  /* Asynchronous Channel 3 Generator Selection bit 7 position. */

/* EVSYS.SYNCCH0  bit masks and bit positions */
#define EVSYS_SYNCCH0_gm  0xFF  /* Synchronous Channel 0 Generator Selection group mask. */
#define EVSYS_SYNCCH0_gp  0  /* Synchronous Channel 0 Generator Selection group position. */
#define EVSYS_SYNCCH00_bm  (1<<0)  /* Synchronous Channel 0 Generator Selection bit 0 mask. */
#define EVSYS_SYNCCH00_bp  0  /* Synchronous Channel 0 Generator Selection bit 0 position. */
#define EVSYS_SYNCCH01_bm  (1<<1)  /* Synchronous Channel 0 Generator Selection bit 1 mask. */
#define EVSYS_SYNCCH01_bp  1  /* Synchronous Channel 0 Generator Selection bit 1 position. */
#define EVSYS_SYNCCH02_bm  (1<<2)  /* Synchronous Channel 0 Generator Selection bit 2 mask. */
#define EVSYS_SYNCCH02_bp  2  /* Synchronous Channel 0 Generator Selection bit 2 position. */
#define EVSYS_SYNCCH03_bm  (1<<3)  /* Synchronous Channel 0 Generator Selection bit 3 mask. */
#define EVSYS_SYNCCH03_bp  3  /* Synchronous Channel 0 Generator Selection bit 3 position. */
#define EVSYS_SYNCCH04_bm  (1<<4)  /* Synchronous Channel 0 Generator Selection bit 4 mask. */
#define EVSYS_SYNCCH04_bp  4  /* Synchronous Channel 0 Generator Selection bit 4 position. */
#define EVSYS_SYNCCH05_bm  (1<<5)  /* Synchronous Channel 0 Generator Selection bit 5 mask. */
#define EVSYS_SYNCCH05_bp  5  /* Synchronous Channel 0 Generator Selection bit 5 position. */
#define EVSYS_SYNCCH06_bm  (1<<6)  /* Synchronous Channel 0 Generator Selection bit 6 mask. */
#define EVSYS_SYNCCH06_bp  6  /* Synchronous Channel 0 Generator Selection bit 6 position. */
#define EVSYS_SYNCCH07_bm  (1<<7)  /* Synchronous Channel 0 Generator Selection bit 7 mask. */
#define EVSYS_SYNCCH07_bp  7  /* Synchronous Channel 0 Generator Selection bit 7 position. */

/* EVSYS.SYNCCH1  bit masks and bit positions */
#define EVSYS_SYNCCH1_gm  0xFF  /* Synchronous Channel 1 Generator Selection group mask. */
#define EVSYS_SYNCCH1_gp  0  /* Synchronous Channel 1 Generator Selection group position. */
#define EVSYS_SYNCCH10_bm  (1<<0)  /* Synchronous Channel 1 Generator Selection bit 0 mask. */
#define EVSYS_SYNCCH10_bp  0  /* Synchronous Channel 1 Generator Selection bit 0 position. */
#define EVSYS_SYNCCH11_bm  (1<<1)  /* Synchronous Channel 1 Generator Selection bit 1 mask. */
#define EVSYS_SYNCCH11_bp  1  /* Synchronous Channel 1 Generator Selection bit 1 position. */
#define EVSYS_SYNCCH12_bm  (1<<2)  /* Synchronous Channel 1 Generator Selection bit 2 mask. */
#define EVSYS_SYNCCH12_bp  2  /* Synchronous Channel 1 Generator Selection bit 2 position. */
#define EVSYS_SYNCCH13_bm  (1<<3)  /* Synchronous Channel 1 Generator Selection bit 3 mask. */
#define EVSYS_SYNCCH13_bp  3  /* Synchronous Channel 1 Generator Selection bit 3 position. */
#define EVSYS_SYNCCH14_bm  (1<<4)  /* Synchronous Channel 1 Generator Selection bit 4 mask. */
#define EVSYS_SYNCCH14_bp  4  /* Synchronous Channel 1 Generator Selection bit 4 position. */
#define EVSYS_SYNCCH15_bm  (1<<5)  /* Synchronous Channel 1 Generator Selection bit 5 mask. */
#define EVSYS_SYNCCH15_bp  5  /* Synchronous Channel 1 Generator Selection bit 5 position. */
#define EVSYS_SYNCCH16_bm  (1<<6)  /* Synchronous Channel 1 Generator Selection bit 6 mask. */
#define EVSYS_SYNCCH16_bp  6  /* Synchronous Channel 1 Generator Selection bit 6 position. */
#define EVSYS_SYNCCH17_bm  (1<<7)  /* Synchronous Channel 1 Generator Selection bit 7 mask. */
#define EVSYS_SYNCCH17_bp  7  /* Synchronous Channel 1 Generator Selection bit 7 position. */

/* EVSYS.ASYNCUSER0  bit masks and bit positions */
#define EVSYS_ASYNCUSER0_gm  0xFF  /* Asynchronous User Ch 0 Input Selection - TCB0 group mask. */
#define EVSYS_ASYNCUSER0_gp  0  /* Asynchronous User Ch 0 Input Selection - TCB0 group position. */
#define EVSYS_ASYNCUSER00_bm  (1<<0)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 mask. */
#define EVSYS_ASYNCUSER00_bp  0  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 0 position. */
#define EVSYS_ASYNCUSER01_bm  (1<<1)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 mask. */
#define EVSYS_ASYNCUSER01_bp  1  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 1 position. */
#define EVSYS_ASYNCUSER02_bm  (1<<2)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 mask. */
#define EVSYS_ASYNCUSER02_bp  2  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 2 position. */
#define EVSYS_ASYNCUSER03_bm  (1<<3)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 mask. */
#define EVSYS_ASYNCUSER03_bp  3  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 3 position. */
#define EVSYS_ASYNCUSER04_bm  (1<<4)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 mask. */
#define EVSYS_ASYNCUSER04_bp  4  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 4 position. */
#define EVSYS_ASYNCUSER05_bm  (1<<5)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 mask. */
#define EVSYS_ASYNCUSER05_bp  5  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 5 position. */
#define EVSYS_ASYNCUSER06_bm  (1<<6)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 mask. */
#define EVSYS_ASYNCUSER06_bp  6  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 6 position. */
#define EVSYS_ASYNCUSER07_bm  (1<<7)  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 mask. */
#define EVSYS_ASYNCUSER07_bp  7  /* Asynchronous User Ch 0 Input Selection - TCB0 bit 7 position. */

/* EVSYS.ASYNCUSER1  bit masks and bit positions */
#define EVSYS_ASYNCUSER1_gm  0xFF  /* Asynchronous User Ch 1 Input Selection - ADC0 group mask. */
#define EVSYS_ASYNCUSER1_gp  0  /* Asynchronous User Ch 1 Input Selection - ADC0 group position. */
#define EVSYS_ASYNCUSER10_bm  (1<<0)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 mask. */
#define EVSYS_ASYNCUSER10_bp  0  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 0 position. */
#define EVSYS_ASYNCUSER11_bm  (1<<1)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 mask. */
#define EVSYS_ASYNCUSER11_bp  1  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 1 position. */
#define EVSYS_ASYNCUSER12_bm  (1<<2)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 mask. */
#define EVSYS_ASYNCUSER12_bp  2  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 2 position. */
#define EVSYS_ASYNCUSER13_bm  (1<<3)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 mask. */
#define EVSYS_ASYNCUSER13_bp  3  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 3 position. */
#define EVSYS_ASYNCUSER14_bm  (1<<4)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 mask. */
#define EVSYS_ASYNCUSER14_bp  4  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 4 position. */
#define EVSYS_ASYNCUSER15_bm  (1<<5)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 mask. */
#define EVSYS_ASYNCUSER15_bp  5  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 5 position. */
#define EVSYS_ASYNCUSER16_bm  (1<<6)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 mask. */
#define EVSYS_ASYNCUSER16_bp  6  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 6 position. */
#define EVSYS_ASYNCUSER17_bm  (1<<7)  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 mask. */
#define EVSYS_ASYNCUSER17_bp  7  /* Asynchronous User Ch 1 Input Selection - ADC0 bit 7 position. */

/* EVSYS.ASYNCUSER2  bit masks and bit positions */
#define EVSYS_ASYNCUSER2_gm  0xFF  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group mask. */
#define EVSYS_ASYNCUSER2_gp  0  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 group position. */
#define EVSYS_ASYNCUSER20_bm  (1<<0)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 mask. */
#define EVSYS_ASYNCUSER20_bp  0  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 0 position. */
#define EVSYS_ASYNCUSER21_bm  (1<<1)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 mask. */
#define EVSYS_ASYNCUSER21_bp  1  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 1 position. */
#define EVSYS_ASYNCUSER22_bm  (1<<2)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 mask. */
#define EVSYS_ASYNCUSER22_bp  2  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 2 position. */
#define EVSYS_ASYNCUSER23_bm  (1<<3)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 mask. */
#define EVSYS_ASYNCUSER23_bp  3  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 3 position. */
#define EVSYS_ASYNCUSER24_bm  (1<<4)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 mask. */
#define EVSYS_ASYNCUSER24_bp  4  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 4 position. */
#define EVSYS_ASYNCUSER25_bm  (1<<5)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 mask. */
#define EVSYS_ASYNCUSER25_bp  5  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 5 position. */
#define EVSYS_ASYNCUSER26_bm  (1<<6)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 mask. */
#define EVSYS_ASYNCUSER26_bp  6  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 6 position. */
#define EVSYS_ASYNCUSER27_bm  (1<<7)  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 mask. */
#define EVSYS_ASYNCUSER27_bp  7  /* Asynchronous User Ch 2 Input Selection - CCL LUT0 Event 0 bit 7 position. */

/* EVSYS.ASYNCUSER3  bit masks and bit positions */
#define EVSYS_ASYNCUSER3_gm  0xFF  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group mask. */
#define EVSYS_ASYNCUSER3_gp  0  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 group position. */
#define EVSYS_ASYNCUSER30_bm  (1<<0)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 mask. */
#define EVSYS_ASYNCUSER30_bp  0  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 0 position. */
#define EVSYS_ASYNCUSER31_bm  (1<<1)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 mask. */
#define EVSYS_ASYNCUSER31_bp  1  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 1 position. */
#define EVSYS_ASYNCUSER32_bm  (1<<2)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 mask. */
#define EVSYS_ASYNCUSER32_bp  2  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 2 position. */
#define EVSYS_ASYNCUSER33_bm  (1<<3)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 mask. */
#define EVSYS_ASYNCUSER33_bp  3  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 3 position. */
#define EVSYS_ASYNCUSER34_bm  (1<<4)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 mask. */
#define EVSYS_ASYNCUSER34_bp  4  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 4 position. */
#define EVSYS_ASYNCUSER35_bm  (1<<5)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 mask. */
#define EVSYS_ASYNCUSER35_bp  5  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 5 position. */
#define EVSYS_ASYNCUSER36_bm  (1<<6)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 mask. */
#define EVSYS_ASYNCUSER36_bp  6  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 6 position. */
#define EVSYS_ASYNCUSER37_bm  (1<<7)  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 mask. */
#define EVSYS_ASYNCUSER37_bp  7  /* Asynchronous User Ch 3 Input Selection - CCL LUT1 Event 0 bit 7 position. */

/* EVSYS.ASYNCUSER4  bit masks and bit positions */
#define EVSYS_ASYNCUSER4_gm  0xFF  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group mask. */
#define EVSYS_ASYNCUSER4_gp  0  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 group position. */
#define EVSYS_ASYNCUSER40_bm  (1<<0)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 mask. */
#define EVSYS_ASYNCUSER40_bp  0  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 0 position. */
#define EVSYS_ASYNCUSER41_bm  (1<<1)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 mask. */
#define EVSYS_ASYNCUSER41_bp  1  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 1 position. */
#define EVSYS_ASYNCUSER42_bm  (1<<2)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 mask. */
#define EVSYS_ASYNCUSER42_bp  2  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 2 position. */
#define EVSYS_ASYNCUSER43_bm  (1<<3)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 mask. */
#define EVSYS_ASYNCUSER43_bp  3  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 3 position. */
#define EVSYS_ASYNCUSER44_bm  (1<<4)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 mask. */
#define EVSYS_ASYNCUSER44_bp  4  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 4 position. */
#define EVSYS_ASYNCUSER45_bm  (1<<5)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 mask. */
#define EVSYS_ASYNCUSER45_bp  5  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 5 position. */
#define EVSYS_ASYNCUSER46_bm  (1<<6)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 mask. */
#define EVSYS_ASYNCUSER46_bp  6  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 6 position. */
#define EVSYS_ASYNCUSER47_bm  (1<<7)  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 mask. */
#define EVSYS_ASYNCUSER47_bp  7  /* Asynchronous User Ch 4 Input Selection - CCL LUT0 Event 1 bit 7 position. */

/* EVSYS.ASYNCUSER5  bit masks and bit positions */
#define EVSYS_ASYNCUSER5_gm  0xFF  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group mask. */
#define EVSYS_ASYNCUSER5_gp  0  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 group position. */
#define EVSYS_ASYNCUSER50_bm  (1<<0)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 mask. */
#define EVSYS_ASYNCUSER50_bp  0  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 0 position. */
#define EVSYS_ASYNCUSER51_bm  (1<<1)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 mask. */
#define EVSYS_ASYNCUSER51_bp  1  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 1 position. */
#define EVSYS_ASYNCUSER52_bm  (1<<2)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 mask. */
#define EVSYS_ASYNCUSER52_bp  2  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 2 position. */
#define EVSYS_ASYNCUSER53_bm  (1<<3)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 mask. */
#define EVSYS_ASYNCUSER53_bp  3  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 3 position. */
#define EVSYS_ASYNCUSER54_bm  (1<<4)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 mask. */
#define EVSYS_ASYNCUSER54_bp  4  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 4 position. */
#define EVSYS_ASYNCUSER55_bm  (1<<5)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 mask. */
#define EVSYS_ASYNCUSER55_bp  5  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 5 position. */
#define EVSYS_ASYNCUSER56_bm  (1<<6)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 mask. */
#define EVSYS_ASYNCUSER56_bp  6  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 6 position. */
#define EVSYS_ASYNCUSER57_bm  (1<<7)  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 mask. */
#define EVSYS_ASYNCUSER57_bp  7  /* Asynchronous User Ch 5 Input Selection - CCL LUT1 Event 1 bit 7 position. */

/* EVSYS.ASYNCUSER6  bit masks and bit positions */
#define EVSYS_ASYNCUSER6_gm  0xFF  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group mask. */
#define EVSYS_ASYNCUSER6_gp  0  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 group position. */
#define EVSYS_ASYNCUSER60_bm  (1<<0)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 mask. */
#define EVSYS_ASYNCUSER60_bp  0  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 0 position. */
#define EVSYS_ASYNCUSER61_bm  (1<<1)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 mask. */
#define EVSYS_ASYNCUSER61_bp  1  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 1 position. */
#define EVSYS_ASYNCUSER62_bm  (1<<2)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 mask. */
#define EVSYS_ASYNCUSER62_bp  2  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 2 position. */
#define EVSYS_ASYNCUSER63_bm  (1<<3)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 mask. */
#define EVSYS_ASYNCUSER63_bp  3  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 3 position. */
#define EVSYS_ASYNCUSER64_bm  (1<<4)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 mask. */
#define EVSYS_ASYNCUSER64_bp  4  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 4 position. */
#define EVSYS_ASYNCUSER65_bm  (1<<5)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 mask. */
#define EVSYS_ASYNCUSER65_bp  5  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 5 position. */
#define EVSYS_ASYNCUSER66_bm  (1<<6)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 mask. */
#define EVSYS_ASYNCUSER66_bp  6  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 6 position. */
#define EVSYS_ASYNCUSER67_bm  (1<<7)  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 mask. */
#define EVSYS_ASYNCUSER67_bp  7  /* Asynchronous User Ch 6 Input Selection - TCD0 Event 0 bit 7 position. */

/* EVSYS.ASYNCUSER7  bit masks and bit positions */
#define EVSYS_ASYNCUSER7_gm  0xFF  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group mask. */
#define EVSYS_ASYNCUSER7_gp  0  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 group position. */
#define EVSYS_ASYNCUSER70_bm  (1<<0)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 mask. */
#define EVSYS_ASYNCUSER70_bp  0  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 0 position. */
#define EVSYS_ASYNCUSER71_bm  (1<<1)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 mask. */
#define EVSYS_ASYNCUSER71_bp  1  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 1 position. */
#define EVSYS_ASYNCUSER72_bm  (1<<2)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 mask. */
#define EVSYS_ASYNCUSER72_bp  2  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 2 position. */
#define EVSYS_ASYNCUSER73_bm  (1<<3)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 mask. */
#define EVSYS_ASYNCUSER73_bp  3  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 3 position. */
#define EVSYS_ASYNCUSER74_bm  (1<<4)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 mask. */
#define EVSYS_ASYNCUSER74_bp  4  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 4 position. */
#define EVSYS_ASYNCUSER75_bm  (1<<5)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 mask. */
#define EVSYS_ASYNCUSER75_bp  5  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 5 position. */
#define EVSYS_ASYNCUSER76_bm  (1<<6)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 mask. */
#define EVSYS_ASYNCUSER76_bp  6  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 6 position. */
#define EVSYS_ASYNCUSER77_bm  (1<<7)  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 mask. */
#define EVSYS_ASYNCUSER77_bp  7  /* Asynchronous User Ch 7 Input Selection - TCD0 Event 1 bit 7 position. */

/* EVSYS.ASYNCUSER8  bit masks and bit positions */
#define EVSYS_ASYNCUSER8_gm  0xFF  /* Asynchronous User Ch 8 Input Selection - Event Out 0 group mask. */
#define EVSYS_ASYNCUSER8_gp  0  /* Asynchronous User Ch 8 Input Selection - Event Out 0 group position. */
#define EVSYS_ASYNCUSER80_bm  (1<<0)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 mask. */
#define EVSYS_ASYNCUSER80_bp  0  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 0 position. */
#define EVSYS_ASYNCUSER81_bm  (1<<1)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 mask. */
#define EVSYS_ASYNCUSER81_bp  1  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 1 position. */
#define EVSYS_ASYNCUSER82_bm  (1<<2)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 mask. */
#define EVSYS_ASYNCUSER82_bp  2  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 2 position. */
#define EVSYS_ASYNCUSER83_bm  (1<<3)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 mask. */
#define EVSYS_ASYNCUSER83_bp  3  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 3 position. */
#define EVSYS_ASYNCUSER84_bm  (1<<4)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 mask. */
#define EVSYS_ASYNCUSER84_bp  4  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 4 position. */
#define EVSYS_ASYNCUSER85_bm  (1<<5)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 mask. */
#define EVSYS_ASYNCUSER85_bp  5  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 5 position. */
#define EVSYS_ASYNCUSER86_bm  (1<<6)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 mask. */
#define EVSYS_ASYNCUSER86_bp  6  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 6 position. */
#define EVSYS_ASYNCUSER87_bm  (1<<7)  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 mask. */
#define EVSYS_ASYNCUSER87_bp  7  /* Asynchronous User Ch 8 Input Selection - Event Out 0 bit 7 position. */

/* EVSYS.ASYNCUSER9  bit masks and bit positions */
#define EVSYS_ASYNCUSER9_gm  0xFF  /* Asynchronous User Ch 9 Input Selection - Event Out 1 group mask. */
#define EVSYS_ASYNCUSER9_gp  0  /* Asynchronous User Ch 9 Input Selection - Event Out 1 group position. */
#define EVSYS_ASYNCUSER90_bm  (1<<0)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 mask. */
#define EVSYS_ASYNCUSER90_bp  0  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 0 position. */
#define EVSYS_ASYNCUSER91_bm  (1<<1)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 mask. */
#define EVSYS_ASYNCUSER91_bp  1  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 1 position. */
#define EVSYS_ASYNCUSER92_bm  (1<<2)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 mask. */
#define EVSYS_ASYNCUSER92_bp  2  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 2 position. */
#define EVSYS_ASYNCUSER93_bm  (1<<3)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 mask. */
#define EVSYS_ASYNCUSER93_bp  3  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 3 position. */
#define EVSYS_ASYNCUSER94_bm  (1<<4)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 mask. */
#define EVSYS_ASYNCUSER94_bp  4  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 4 position. */
#define EVSYS_ASYNCUSER95_bm  (1<<5)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 mask. */
#define EVSYS_ASYNCUSER95_bp  5  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 5 position. */
#define EVSYS_ASYNCUSER96_bm  (1<<6)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 mask. */
#define EVSYS_ASYNCUSER96_bp  6  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 6 position. */
#define EVSYS_ASYNCUSER97_bm  (1<<7)  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 mask. */
#define EVSYS_ASYNCUSER97_bp  7  /* Asynchronous User Ch 9 Input Selection - Event Out 1 bit 7 position. */

/* EVSYS.ASYNCUSER10  bit masks and bit positions */
#define EVSYS_ASYNCUSER10_gm  0xFF  /* Asynchronous User Ch 10 Input Selection - Event Out 2 group mask. */
#define EVSYS_ASYNCUSER10_gp  0  /* Asynchronous User Ch 10 Input Selection - Event Out 2 group position. */
#define EVSYS_ASYNCUSER100_bm  (1<<0)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 mask. */
#define EVSYS_ASYNCUSER100_bp  0  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 0 position. */
#define EVSYS_ASYNCUSER101_bm  (1<<1)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 mask. */
#define EVSYS_ASYNCUSER101_bp  1  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 1 position. */
#define EVSYS_ASYNCUSER102_bm  (1<<2)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 mask. */
#define EVSYS_ASYNCUSER102_bp  2  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 2 position. */
#define EVSYS_ASYNCUSER103_bm  (1<<3)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 mask. */
#define EVSYS_ASYNCUSER103_bp  3  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 3 position. */
#define EVSYS_ASYNCUSER104_bm  (1<<4)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 mask. */
#define EVSYS_ASYNCUSER104_bp  4  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 4 position. */
#define EVSYS_ASYNCUSER105_bm  (1<<5)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 mask. */
#define EVSYS_ASYNCUSER105_bp  5  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 5 position. */
#define EVSYS_ASYNCUSER106_bm  (1<<6)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 mask. */
#define EVSYS_ASYNCUSER106_bp  6  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 6 position. */
#define EVSYS_ASYNCUSER107_bm  (1<<7)  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 mask. */
#define EVSYS_ASYNCUSER107_bp  7  /* Asynchronous User Ch 10 Input Selection - Event Out 2 bit 7 position. */

/* EVSYS.ASYNCUSER11  bit masks and bit positions */
#define EVSYS_ASYNCUSER11_gm  0xFF  /* Asynchronous User Ch 11 Input Selection - TCB1 group mask. */
#define EVSYS_ASYNCUSER11_gp  0  /* Asynchronous User Ch 11 Input Selection - TCB1 group position. */
#define EVSYS_ASYNCUSER110_bm  (1<<0)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 mask. */
#define EVSYS_ASYNCUSER110_bp  0  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 0 position. */
#define EVSYS_ASYNCUSER111_bm  (1<<1)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 mask. */
#define EVSYS_ASYNCUSER111_bp  1  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 1 position. */
#define EVSYS_ASYNCUSER112_bm  (1<<2)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 mask. */
#define EVSYS_ASYNCUSER112_bp  2  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 2 position. */
#define EVSYS_ASYNCUSER113_bm  (1<<3)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 mask. */
#define EVSYS_ASYNCUSER113_bp  3  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 3 position. */
#define EVSYS_ASYNCUSER114_bm  (1<<4)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 mask. */
#define EVSYS_ASYNCUSER114_bp  4  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 4 position. */
#define EVSYS_ASYNCUSER115_bm  (1<<5)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 mask. */
#define EVSYS_ASYNCUSER115_bp  5  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 5 position. */
#define EVSYS_ASYNCUSER116_bm  (1<<6)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 mask. */
#define EVSYS_ASYNCUSER116_bp  6  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 6 position. */
#define EVSYS_ASYNCUSER117_bm  (1<<7)  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 mask. */
#define EVSYS_ASYNCUSER117_bp  7  /* Asynchronous User Ch 11 Input Selection - TCB1 bit 7 position. */

/* EVSYS.ASYNCUSER12  bit masks and bit positions */
#define EVSYS_ASYNCUSER12_gm  0xFF  /* Asynchronous User Ch 12 Input Selection - ADC0 group mask. */
#define EVSYS_ASYNCUSER12_gp  0  /* Asynchronous User Ch 12 Input Selection - ADC0 group position. */
#define EVSYS_ASYNCUSER120_bm  (1<<0)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 mask. */
#define EVSYS_ASYNCUSER120_bp  0  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 0 position. */
#define EVSYS_ASYNCUSER121_bm  (1<<1)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 mask. */
#define EVSYS_ASYNCUSER121_bp  1  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 1 position. */
#define EVSYS_ASYNCUSER122_bm  (1<<2)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 mask. */
#define EVSYS_ASYNCUSER122_bp  2  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 2 position. */
#define EVSYS_ASYNCUSER123_bm  (1<<3)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 mask. */
#define EVSYS_ASYNCUSER123_bp  3  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 3 position. */
#define EVSYS_ASYNCUSER124_bm  (1<<4)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 mask. */
#define EVSYS_ASYNCUSER124_bp  4  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 4 position. */
#define EVSYS_ASYNCUSER125_bm  (1<<5)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 mask. */
#define EVSYS_ASYNCUSER125_bp  5  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 5 position. */
#define EVSYS_ASYNCUSER126_bm  (1<<6)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 mask. */
#define EVSYS_ASYNCUSER126_bp  6  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 6 position. */
#define EVSYS_ASYNCUSER127_bm  (1<<7)  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 mask. */
#define EVSYS_ASYNCUSER127_bp  7  /* Asynchronous User Ch 12 Input Selection - ADC0 bit 7 position. */

/* EVSYS.SYNCUSER0  bit masks and bit positions */
#define EVSYS_SYNCUSER0_gm  0xFF  /* Synchronous User Ch 0 - TCA0 group mask. */
#define EVSYS_SYNCUSER0_gp  0  /* Synchronous User Ch 0 - TCA0 group position. */
#define EVSYS_SYNCUSER00_bm  (1<<0)  /* Synchronous User Ch 0 - TCA0 bit 0 mask. */
#define EVSYS_SYNCUSER00_bp  0  /* Synchronous User Ch 0 - TCA0 bit 0 position. */
#define EVSYS_SYNCUSER01_bm  (1<<1)  /* Synchronous User Ch 0 - TCA0 bit 1 mask. */
#define EVSYS_SYNCUSER01_bp  1  /* Synchronous User Ch 0 - TCA0 bit 1 position. */
#define EVSYS_SYNCUSER02_bm  (1<<2)  /* Synchronous User Ch 0 - TCA0 bit 2 mask. */
#define EVSYS_SYNCUSER02_bp  2  /* Synchronous User Ch 0 - TCA0 bit 2 position. */
#define EVSYS_SYNCUSER03_bm  (1<<3)  /* Synchronous User Ch 0 - TCA0 bit 3 mask. */
#define EVSYS_SYNCUSER03_bp  3  /* Synchronous User Ch 0 - TCA0 bit 3 position. */
#define EVSYS_SYNCUSER04_bm  (1<<4)  /* Synchronous User Ch 0 - TCA0 bit 4 mask. */
#define EVSYS_SYNCUSER04_bp  4  /* Synchronous User Ch 0 - TCA0 bit 4 position. */
#define EVSYS_SYNCUSER05_bm  (1<<5)  /* Synchronous User Ch 0 - TCA0 bit 5 mask. */
#define EVSYS_SYNCUSER05_bp  5  /* Synchronous User Ch 0 - TCA0 bit 5 position. */
#define EVSYS_SYNCUSER06_bm  (1<<6)  /* Synchronous User Ch 0 - TCA0 bit 6 mask. */
#define EVSYS_SYNCUSER06_bp  6  /* Synchronous User Ch 0 - TCA0 bit 6 position. */
#define EVSYS_SYNCUSER07_bm  (1<<7)  /* Synchronous User Ch 0 - TCA0 bit 7 mask. */
#define EVSYS_SYNCUSER07_bp  7  /* Synchronous User Ch 0 - TCA0 bit 7 position. */

/* EVSYS.SYNCUSER1  bit masks and bit positions */
#define EVSYS_SYNCUSER1_gm  0xFF  /* Synchronous User Ch 1 - USART0 group mask. */
#define EVSYS_SYNCUSER1_gp  0  /* Synchronous User Ch 1 - USART0 group position. */
#define EVSYS_SYNCUSER10_bm  (1<<0)  /* Synchronous User Ch 1 - USART0 bit 0 mask. */
#define EVSYS_SYNCUSER10_bp  0  /* Synchronous User Ch 1 - USART0 bit 0 position. */
#define EVSYS_SYNCUSER11_bm  (1<<1)  /* Synchronous User Ch 1 - USART0 bit 1 mask. */
#define EVSYS_SYNCUSER11_bp  1  /* Synchronous User Ch 1 - USART0 bit 1 position. */
#define EVSYS_SYNCUSER12_bm  (1<<2)  /* Synchronous User Ch 1 - USART0 bit 2 mask. */
#define EVSYS_SYNCUSER12_bp  2  /* Synchronous User Ch 1 - USART0 bit 2 position. */
#define EVSYS_SYNCUSER13_bm  (1<<3)  /* Synchronous User Ch 1 - USART0 bit 3 mask. */
#define EVSYS_SYNCUSER13_bp  3  /* Synchronous User Ch 1 - USART0 bit 3 position. */
#define EVSYS_SYNCUSER14_bm  (1<<4)  /* Synchronous User Ch 1 - USART0 bit 4 mask. */
#define EVSYS_SYNCUSER14_bp  4  /* Synchronous User Ch 1 - USART0 bit 4 position. */
#define EVSYS_SYNCUSER15_bm  (1<<5)  /* Synchronous User Ch 1 - USART0 bit 5 mask. */
#define EVSYS_SYNCUSER15_bp  5  /* Synchronous User Ch 1 - USART0 bit 5 position. */
#define EVSYS_SYNCUSER16_bm  (1<<6)  /* Synchronous User Ch 1 - USART0 bit 6 mask. */
#define EVSYS_SYNCUSER16_bp  6  /* Synchronous User Ch 1 - USART0 bit 6 position. */
#define EVSYS_SYNCUSER17_bm  (1<<7)  /* Synchronous User Ch 1 - USART0 bit 7 mask. */
#define EVSYS_SYNCUSER17_bp  7  /* Synchronous User Ch 1 - USART0 bit 7 position. */

That really confuses me.

 

Seems simple.  

 

I want to the output of LUT0 to generate an event on async channel 0 and timer B0 to use it:

 

	// First pick a generator--LUT0
	EVSYS_ASYNCCH0 = EVSYS_ASYNCCH0_CCL_LUT0_gc;  // Configurable Custom Logic LUT0 
	
	// ASYNCHUSER0 is TCB0 (Timer/Counter B 0
	// Set that peripheral to use ASYNC channel 0
	EVSYS.ASYNCUSER0 = EVSYS_ASYNCUSER0_ASYNCCH0_gc;	 // Timer/Counter B0  

I can see no purpose for all those #defines.  Which maybe means I'm missing something about how to configure the event system.

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 are autogenerated from the .atdf part description files (XML) so they should have everything the part contains.

Can you elaborate on the .atdf file is, and why it's likely to be more accurate than the spec?

 

Am I likely to get a prompt response if I post an "issue" (can AC1 and AC2 provide inputs to the LUT) on the Microchip support site?

 

Thanks

 

 

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I'm missing the relevancy. 

 

The #endif for the #if !defined (__ASSEMBLER__) is on line 2225 in iotn1614.h.   The confusing #defines and enums are above that line, so they apply for C language 

 

  

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davethomaspilot wrote:
Am I likely to get a prompt response if I post an "issue" (can AC1 and AC2 provide inputs to the LUT) on the Microchip support site?

 

It may be faster to experiment yourself, after all the datasheet has all the needed info. Anyway, even if the AC1/2 outputs can't be connected to the LUT directly, they can probably be connected indirectly via the Event System.

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davethomaspilot wrote:

The #endif for the #if !defined (__ASSEMBLER__) is on line 2225 in iotn1614.h.   The confusing #defines and enums are above that line, so they apply for C language 

The point is that for something like AC1 CTRLA you will find two definitions of the same thing. One lets you access it as AC1.CTRLA and the other as AC1_CTRLA. The former only works for C/C++ while the latter can be used for all of C/C++/Asm. To a certain extent it's purely a matter of personal taste which you might prefer but, because the C/C++ struct dot notation might benefit if you are setting two registers in the same block (it'll load the base into Z then do ST Z+n accesses) it might be "better" to use the C/C++ nomenclature when you can.

davethomaspilot wrote:
Can you elaborate on the .atdf file is, and why it's likely to be more accurate than the spec?
It really requires someone from Atmel/Microchip (Morten etc) to give you chapter and verse on this but I believe the ATDF are actually part of the chip production itself. Either it's an input (you put that into the "silicon machine" and out pops the chips) or it's an output (the chip is specified then out pops an ATDF from the silicon machine) but either way experience shows that the ATDF files are an "exact description" of what you have got. They (XML textual description of everything) are then used in at least two ways. One is that Atmel have a .h generator that reads them as input and churns out .h. So if things are in error or missing from any device .h file it's a direct consequence of it being wrong/missing in the ATDF. Also the AS7 simulator/debugger uses them as an input too. So when you debug and it shows you the register file in a chip and all the bits in all the registers the bit positions, names and register addresses are all being taken from the ATDF file.

 

As I say, experience (many many times) here has shown that often the ATDF show the true picture about a chip when the datasheet itself has certain errors, omissions, white lies and mis-truths.

 

(oh and both my Tiny and Mega packs/ATDF ARE out of date in my copy of AS7!)

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clawson wrote:
so this does not include the 0x0C, 0x0D, 0x0E values for AC1, TCB1, AC2 that the datasheet seems to think are also available.

 

PS caveat - I don't know if I have the latest pack (using 1.3.229) - it's vaguely possible this may have been changed/corrected in a later issue.

TCB1 is mentioned in the year '19 update :

http://packs.download.atmel.com/#collapse-Atmel-ATtiny-DFP-pdsc

 

"Dare to be naïve." - Buckminster Fuller

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I do wish AS7 were able to pull packs in the Pack Manager through a corporate firewall - but ours seems intent on blocking an update :-(

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clawson wrote:
often the ATDF show the true picture about a chip

 

They show a picture that is very close to the truth. I've experimented a lot with these chips, and found that the simulator that comes with AS7 offers an even closer picture.

 

For example, all the available documents (datasheet, iotn1614.h, ATtiny1614.atdf) say that the tiny1614 has 2 ports, A and B. The simulator says there is a PORTC:

 

In real hardware, this port isn't externally connected, but appears to exist internally. Not all functionality seems to work, though... I like to experiment with this kind of undocumented stuff, even if it can't be used in practicesmiley

After all, being undocumented means it can be changed in future silicon revisions.

 

Last Edited: Tue. Jan 14, 2020 - 02:57 PM
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Clawson,

 

I understand that some of the references work only in C/C++.   My point is that I'm working in C++ and that the confusing ones are not specific to assembler.

 

As I mentioned, I did update the Tiny and Megapacks in my copy AS7.  Where do I find the .atdf you are referencing?

 

So, there are now two topics being discussed in this thread

 

1)   Can AC1, TCB1, and AC2 be used as inputs to the LUTS.  Spec says yes, iotn1614.h enum does not include them.

2)   Are all those #defines for ASYNC and SYNC registers of the EVTSYS just bogus (have no conceviable purpose)?

 

On 1)

 

I can't think of a way to use the simulator to verify this.  I want to use analog comparator outputs as inputs to the LUT.   

 

The inputs of the comparators are analog signals--the simulator won't handle that.

 

The outputs of the comparators (STATE) are read only.  I don't think the simulator can overwrite RO bits, can it?

 

So, how would I use the simulator to determine if (for example) writing 0xc (AC1) to the higher order nibble of LUT CTRLB really does connect the output of analog comparator 1?

 

Seems like I'll just have to code it and use real hardware to find out.

 

 

 

 

 

 

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Found the .atdf.

 

 

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davethomaspilot wrote:

First anomaly I saw was that iotn1614.h is NOT referenced in avr/io.h [...]

But,  I hacked io.h to add an include iotn1614.h:

This should be rectified by the respective device-specs file, and they even explain how:

device-specs/specs-atmega8 wrote:

# AVR-LibC's avr/io.h uses the device specifying macro to determine
# the name of the device header.  For example, -mmcu=atmega8a triggers
# the definition of __AVR_ATmega8A__ and avr/io.h includes the device
# header 'iom8a.h' by means of:
#
#     ...
#     #elif defined (__AVR_ATmega8A__)
#     #  include <avr/iom8a.h>
#     #elif ...
#
# If no device macro is defined, AVR-LibC uses __AVR_DEV_LIB_NAME__
# as fallback to determine the name of the device header as
#
#     "avr/io" + __AVR_DEV_LIB_NAME__ + ".h"
#
# If you provide your own specs file for a device not yet known to
# AVR-LibC, you can now define the hook macro __AVR_DEV_LIB_NAME__
# as needed so that
#
#     #include <avr/io.h>
#
# will include the desired device header.  For ATmega8A the supplement
# to *cpp_avrlibc would read
#
#     -D__AVR_DEV_LIB_NAME__=m8a

 

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Last Edited: Tue. Jan 14, 2020 - 03:14 PM
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this was already answered--twice.  My bad.  But, wasn't really the main point of the post.

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davethomaspilot wrote:
Where do I find the .atdf you are referencing?
That's why I took the picture in #7 to include a tooltip ;-)

 

 

but I guess you found it (and you probably aren't stuck with 1.3.229 either!)

 

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The datasheet is not a perfect document. Go take a look at a tiny414 and see what that table with the discrepancy looks like. 9 times out of 10, the header will be correct and another datasheet of a device similar usually reveals a datasheet error (they have a copy/paste problem that may never go away).

 

They also most likely generate the headers 'blindly', so in the case of some things like the channel selection where bits do not come into play you end up with defines that make no sense to use. So ignore them.

 

>My point is that I'm working in C++

 

You can also do your own thing and forget the headers (or just selectively forget parts of it)-

https://github.com/cv007/ATTiny416XplainedNano/blob/master/Evsys.hpp

with a little bit of code you can come up with something that will prevent you from make connections that are not possible.

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Might be able to do an end run around the firewall.

A router can run a web proxy to cache Atmel device packs; else, there's WSL in Windows 10.

 

https://wiki.squid-cache.org/SquidFaq/ConfiguringSquid#How_do_I_configure_Squid_to_work_behind_a_firewall.3F

Squid 4.9 configuration file (search for 'period')

both due to OpenWrt Project: packages:index:network---web-servers-proxies

Tutorials - DD-WRT Wiki

[3/4 page]

Installable Packages

WSL - Windows Subsystem for Linux

 

"Dare to be naïve." - Buckminster Fuller

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davethomaspilot wrote:
2)   Are all those #defines for ASYNC and SYNC registers of the EVTSYS just bogus (have no conceviable purpose)?

Basically yes, they are meaningless and useless, because these bits have no individual function, they only make sense as a group.

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Since Morten is on vacation I'll give it a try.

 

The ATDF file is what all the device support is based on. Header files, assembler include files, IO-view in Studio, START,... The ATDF is used whenever we need to lookup device specific information. Since it is initially created by the IC Engineering department it is generally quite accurate.
Yes, we generate bit masks and bit position for all bits, so there might be a lot of unnecessary definitions. In this case we think it's better to have a couple too many than too few. Bits are cheap, and it makes the generator more generic. It's also quite impossible for us to guess which definitions you freaks find useful or not. 

 

The simulator in Studio is even more accurate because it is made up of the same RTL that is used for the actual chip. One change we do to the simulator models compared to the real chip is that we try to make all registers writable. This means that you are able to write registers like the ADC result register and interrupt flags. Settings interrupt flags to 1 in the IO-view will actually trigger interrupts. So by writing to the ADC result register and setting the ADC result ready flag you can mimic the analog parts of an AD-conversion.

 

Yes, tiny1614 has PORTC. tiny1614 is actually a tiny1617 in a smaller package, which means that there is no pins for the PORTC bits to connect to. But the registers are still there, and I bet there are a lot of clever freaks here which can make some ingenious use of this.

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je_ruud wrote:
One change we do to the simulator models compared to the real chip is that we try to make all registers writable.
Using the I/O View with the Simulator - - Simulator

 

"Dare to be naïve." - Buckminster Fuller

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je_ruud wrote:
I'll give it a try.
I love this kind of insight! It's a real privilege to have access to this kind of thing.

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je_ruud wrote:

Yes, tiny1614 has PORTC. tiny1614 is actually a tiny1617 in a smaller package, which means that there is no pins for the PORTC bits to connect to. But the registers are still there, and I bet there are a lot of clever freaks here which can make some ingenious use of this.

Toggling attached bits fast and use the internal wiring as radio transmitter?

 

Write some value to them bits, let them float for some time, then read them back and thereby collapse the entangled quantum state. You just turned your AVR into a 8-bit quantum computer.

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Last Edited: Tue. Jan 14, 2020 - 05:16 PM
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It's just the Norwegian shyness and Janteloven in action. But then I feel Morten is much better than me in wording this.

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>tiny1614 is actually a tiny1617 in a smaller package

 

Well, that explains the copy/paste thing. I imagine someone behind the wheel of the datasheet machine getting confused about what the mcu actually is (or knows too much). In this case, a copy/paste from a 32/1617 to a 1614, except all the headers for the 2/4/8/1614 and 32/1617 are all the same for the CCL LUT INSEL values. So, then the question is how did the table end up in the 32/1617? If you grep for those values in the tiny or mega dfp folders nothing comes up. So maybe the tables are correct, but the failure is somewhere else in the generation of the headers for the 32/1617 and 1614. In any case, when in doubt, test it out.

 

I may be giving bad advice about checking other datasheets- instead of just looking up/down the column for a similar 0/1 device (same pin count), may also need to look sideways I guess (same flash size). 

 

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Fortunately, it looks like the CCL LUTS actually DO support the additional peripherals, despite the fact that the #defines for them are not in the iotn1614.h.

 

The debugger GUI does recognize them.  For INSEL1 values of 0 to 0xb (the ones in the header file and .atdf), the name of the associated peripheral shows up in the IO view.  For 0xc to 0xe, the label is blank.

 

But, I configured INSEL1 to be 0xe (AC2 out) and enabled the output of the CCL to the associated pin on the device.  I can cause the the comparator to toggle by either by driving the AINP0 high, or changing the AINN0 input (it's connected to a DAC output).

 

Doing either causes the pin that's connected to the LUT output to toggle.

 

The INSSEL0 is AC0.  I can do the same with it.  (The truth register for the LUT is a logical OR).

 

So, it appears this is an example of an (apparently) rare case where the spec is correct, but the header file and .atdf are incomplete.

 

Next, I'll move on to trying out the EVTSYS configuration, and ignore unhelpful #defines in the header file.  

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The #defines I referenced made me question my understanding of how to configure the user channels.  Usually, I've found the .h file is useful in getting the configuration right.

 

It's not like there are bit masks and bit position #defines for every bit in every register in the device.  But, for some reason, that was done for every one of the SYNCH and ASSYNC registers.  That's "why I asked why".

 

There must be a reason those #defines were generated.  Either someone in the generation methodology didn't understand how to configure them, or I don't.

 

 

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So, apparently the EVTSYS works like I thought--got things working.

 

Thanks for the replies.  The thread got too long, so I thought I'd summarize the key points,  in case someone chases something similar and reads the thread.

 

Here's what I learned (or at least what I learned that I consider relevant to my original question).  Please correct if I misunderstood or have overstated some points.

 

 

  • The device specific headers are (at least in part) automatically generated.  So, some of the header file content may be meaningless--there may be #defines for symbolic constants that really aren't at all useful.  That doesn't necessarily mean the spec is wrong or you don't understand the spec.
  • Not all device specific headers are explicitly included in io.h.  Many are, but not all.  Omission doesn't imply the header file is preliminary.
  • It's not uncommon for the spec to be wrong!!  Apparently, even if it documents features that might not reallly exist in the hardware (the CCL example). 
  • It's common (and recommended)  practice to trust the .adtf file instead of the published specification, since those come more directly from developers than the specification document.
  • In the CCL example, the specification is actually correct.  The #define/enums in the .adtf file and header files exclude several valid values for the EVSYS ASYNC and SYNC registers (the one's I need, as Murphy would have it).

 

I'll finish as I started--I'm really impressed by what can be done with CCL and EVTSYS.  Using these, I can perform combinatorial logic on the outputs of the analog comparators, and get the frequency (from TCB0) of logical output edges with no code or ISR required! 

 

I'd planned an ISR for TCB0 that would keep a running average of the measured frequency and start a second timer that would delay slightly to define an optimal time when all the comparator outputs should be sampled. But, now I'm thinking I can use another  EVTSYS channel for that too.

 

Fun stuff!

 

Thanks.