Unwanted compare flag B in compare A interrupt.

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I'm using Atmega32 8MHZ ( AVR studio simulator) and I  added OCR1A compare match interrupt for timer 1 and also comapre match for timer0

 

.cseg
.org 0x00
rjmp START
.org 0x0E
rjmp T1_CMA_ISR
.org 0x14
rjmp T0_CM_ISR
;=======================================
.org 0x100
START:
    ldi r16, high(65536-200)
	out OCR1AH, r16
	ldi r16, low(65536-200)
	out OCR1AL, r16
	
	ldi r16, 0x00
	out TCCR1A, r16
	ldi r16, (1<<WGM12) | (1<<CS10)
	out TCCR1B, r16

	ldi r16, (1<<OCIE1A) | (1<<OCIE0)
	out TIMSK, r16
	
	sei

MLOOP:
	rjmp MLOOP
;=======================================	
T1_CMA_ISR:
	in r17, TCNT1L
	in r18, TCNT1H

	reti
;=======================================
T0_CM_ISR:
	
	in r17, TCNT0
	reti

So when Compare A match interrupt is starting I see that OCF1B flag is set instead of OCF1A flag in TIFR register. 
Can somebody explain why? 

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You haven't cleared the ocf1b flag.
The ocf1a flag gets cleared by hardware when the isr is entered.

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I see the same but isn't this what you might expect? You wouldn't expect to see 0CF1A set in the COMPARE_A handler because:

 

 

So OCF1A is already cleared as part of the mechanism that brought it into the T1_CMA_ISR: handler. 

 

So the only real mystery here is why OCF1B is set too. Well the B comparison stuff will sill happen as the timer runs so when TCNT1 matches OCR1B and the timer is running the OCF1B flag will be set. as OCR1B defaults to 0x0000 I guess this happens early. Presumably if you set OCR1B to a value that is HIGHER than OCR1A (0xFFFF say?) then it won't be set when you enter the ISR?

 

EDIT: yup, just tried that:

START:
	ser r16
	out OCR1BH, r16
	out OCR1BL, r16
    ldi r16, high(65536-200)
	out OCR1AH, r16
	ldi r16, low(65536-200)
	out OCR1AL, r16

(added the 3 lines after START:) and OCF1B is NOT set when it enters the OCR1A interrupt.

 

Presumably the surprise to you here is the fact that the B channel flagging mechanism actually operates even though you haven't "switched it on"? But that's the point - it does it anyway - the only "switching on" is to tell the CPU whether to take special action when the flag does get set (by setting the OCIE1B bit)

Last Edited: Mon. Jan 13, 2020 - 02:43 PM
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So I set 

OCR1BH

and 

OCR1BL

registers with same values as OCR1AH and OCR1AH ,
Added compare B interrupt ISR,
BUT! I did not set OCIE1B flag in TIMSK register, So.. CPU will set compare B bit flag , BUT because I did not set OCIE1B flag nothing will happen, CPU just setting bit, nothing else..
right? 

 

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The timer sets the compare flag, not the cpu! Otherwise, yes. If you don’t enable the interrupt, the cpu will not respond.

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Yes yes Timer not CPU, sorry. Thanks