SAME53, how to use DPLL to generate 120MHz fCPU

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I have my custom board with SAME53J19A in TQFP64 package, Silicon Revision A.

I managed to use Atmel Start and generate 120MHz clocks via DPLL0:  it uses XOSC32K as reference and must be checked "Lock Bypass" (due to Errata 2.13.1).


Then I decided to use XOSC1=12MHz as reference for DPLL0.

I found what describes this thread:

= that Atmel Start doesn't allow to select the XOSC1 directly as reference, because it ignores the "Clock Divider" value (internal prescaller needed for the 12MHz input from XOSC1).


So I decided to do it like others (in the thread)

= to use one of Generic Clock Generators, bring XOSC1 to it, divide /12, and the result 1MHz select as reference in DPLL0.


While others describe they used Gen_2 or Gen_3 and divide /12 and it worked, in my case it did not.


I tried several configuration variants, approximately in this order (and none worked):

1) enabled oscillator XOSC1=12MHz, goes to Gen_8 that divides /4 = 3MHz, this frequency is used as reference for DPLL0; in DPLL0 are checked "Lock Bypass" and also "Wake Up Fast"

2) XOSC1_12MHz --> Gen_8 divides /8 = 1.5MHz --> DPLL0_x80 = 120MHz;

3) replaced Gen_8 with Gen_4

4) replaced Gen_4 with Gen_2, div /12 = 1MHz

5) changed Gen_2 settings, checked "Divide Selection", DIV=7, so the frequency is divided by 2^(N+1), ie 2^8 = div 256, it makes frequency 46875 Hz  (I wanted frequency similar to 32768 that worked ok)

6) instead of DPLL0 used DPLL1, the same settings



(1) I thought any [Gen] can be used to divide 12MHz to frequency in range 32kHz .. 3.2MHz as stated in datasheet, so I chosed 3MHz (expecting lowest jitter possible)

(2) I thought 3MHz is too close to upper limit, I was warried about getting away of PLL regulation

(3),(4),(5) I thought possibly not all [Gen]s can be used to bring clocks to DPLLs, also tried to lower the frequency again, ended up with [Gen_2] that "should work", according to the thread above

(6) I thought possibly DPLL0 is faulty so tried the second


As I wrote, none of these CLOCK configurations worked.

In all cases there was some stable, but WRONG frequency generated - I think so, because my firmware included USB_CDC driver, and printing to virtual COM was possible;

state of 32b RTC timer (@32768) was captured before and after long delay (12mil SysTick ticks) and printed.

So, I calculated that during experiments (1)..(4) the frequency was about 39MHz, and (5),(6) it was about 83MHz.


I suppose XOSC1 is not a problem, amplitudes on XTAL pads are high (3V and 2V), frequency is stable 12 MHz, never observed any changes.


What is wrong ?

Could anybody share any .atstart file containing  XOSC1 --> DPLL0 making 120 MHz (that really works) ?

or screenshots of XOSC / Gen / DPLL settings


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I have a ATSAMD51P20A and the attached works. The crystal is 16MHz and gen 2 is used /16.   GCLK/IO[0] is output on PB14.



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Hi Lajon (/Lars),

I tried a similar configuration before and it didn't work, the only difference was XOSC1 had Start-Up time 31us (you have 15625us),

Gen_2 had divider /12 (you have /16 as your XTAL is 16MHz, but my 12MHz), and DPLL0 had checked "Lock Bypass" and "Wake Up Fast" (you have them not-checked).


Anyway, I tried to copy your settings exactly, excluding only I have Gen_2 divider /12 (for XTAL 12MHz), but it doesn't work.

Unlike my other configurations, this time USB-enumeration didn't even start.

I suppose that for some reason DPLL0 is unable to Lock and because "Lock Bypass" was not-checked => instable output clock of DPLL0 is gated-out => no clock available for CPU.