I thought my problem from the topic "strange reset" was fixed, I was wrong.
My project, a webserver seems to reset randomly.
I thought it was tack overflow so I connected my JTAGICE to the ATMEGA128 with a data breakpoint at 0x0100.
The program restarts at 0x0000 but the only time the STACKEND is written, is when CVAVR clears the RAM at init, from the .lst file:
000140 93ed ST X+,R30
000141 9701 SBIW R24,1
000142 f7e9 BRNE __CLEAR_SRAM
I enabled watchdog and brownout at 4V.
I'm lost, any suggestions to what might be the problem and/ or how to locate it?
Thanks in advance.