ADC/AREF/ISP - unused pins

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good day!

 

ATmeg328 datasheet

 

5.2.8. AREF
AREF is the analog reference pin for the A/D Converter.

 

5.2.9. ADC[7:6] (TQFP and VFQFN Package Only)

In the TQFP and VFQFN package, ADC[7:6] serve as analog inputs to the A/D converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
 

inner pull-up is no exist ... 

what to do with unused these pins (AREF & ADC)?

 

I suppose that everything can be grounded, but how is it correct within the framework of the "AVR-architecture"?

 

thank

 

p.s.

similar to what to do with the pins of the ISP connector? (they are used only for programming, do not participate in the circuit)

if I'm wrong, correct this and do not criticize :o)

Last Edited: Thu. Dec 26, 2019 - 09:27 AM
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AREF you can leave floating (ie no connection) if you are not using the ADC. The analog inputs are also port pins, so you can enable the pullups or set as outputs.

 

RESET has a pullup resistor, the other pins float.

 

 

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You can let all three of those pins float, I usually connect a 100nf cap to gnd on the AREF pin, it should never be connected to gnd or vcc.

On the M328p, ADC 6&7 are analog only pins, they can be left floating if not used.

Jim

 

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highlighting in red, what kind of mechanism, what function does it carry?

Attachment(s): 

if I'm wrong, correct this and do not criticize :o)

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It is called a ‘transmission gate’. It is basically the cmos version of a relay.

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I do care what it's called !!! smiley

What function does it have?
 

What does it do, how does it function, what signals does it pass to, where does it not pass? in fact, we have a 4-pole ... with incomprehensible functionality

 

thank 

if I'm wrong, correct this and do not criticize :o)

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sunjob wrote:
What does it do,

It is a transmistion gate, so when the control signal, coming from the top is high, it passes the signal on the left side to the right, actually, it will pass both directions, but in this case....

In this use, when SLEEP is low (not sleeping), the signal at the input pin passes through to the input latch, when SLEEP is high (Sleeping)

The input pin is disconnected and the fet grounds the input to prevent any noise from effecting the input latch.

Does that help?

It is explained in the text of the port pin description, frankly, I find the schematic most helpful, not all chip makers do this.

Jim

 

 

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Last Edited: Fri. Dec 27, 2019 - 04:13 PM
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for me, best help, this sheme smiley

 

Transmission gate

 

thank

if I'm wrong, correct this and do not criticize :o)

Last Edited: Sat. Dec 28, 2019 - 06:59 AM
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As i said, the cmos equivalent of a relay!

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... cmos equivalent of a relay...

does not say anything, for understanding, especially since we have 4-poles (four-pole), and the above diagram gives a complete picture of the work, the functionality of this element

 

thank

if I'm wrong, correct this and do not criticize :o)

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I think something is getting lost in translation as a transmission gate is not 4 POLE. There may be 4 NODES, not POLES. 

 

 

The 4016 is the classic 4000 series cmos device with four of these transmission gates. See how they are drawn. Clearly single POLE.

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Kartman wrote:

The analog inputs are also port pins, so you can enable the pullups or set as outputs.

Note ADC[7:6] are ADC only, no GPIO.

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5.2.8. AREF

5.2.9. ADC[7:6] (TQFP and VFQFN Package Only)

if I'm wrong, correct this and do not criticize :o)

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Kartman wrote:
The 4016 is the classic 4000 series cmos device with four of these transmission gates.

Forgive my noobish question, my electronics is entirely self taught.

A "transmission gate" and an "analog switch" are the same circuit, right? That is, a NMOS and a PMOS in parallel, plus an inverter that keeps their gates in a complementary state.

Last Edited: Fri. Jan 3, 2020 - 03:51 PM
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Indeed they are. Just like Zoolander all over again!