This query is driven by a starting design using M4808/9 with multiple UARTs, but I think it is actually somewhat more general than that.
I am looking at a serial channel that supports both SPI and async serial since these UARTs are capable of working in either mode. That is, I am looking at a channel that might contain BOTH SPI slaves and async peripherals.
I do understand that async does not have an explicit master/slave relationship. Thus, something would have to be done to provide the equivalent of a chip select and tri-state functionality at the peripheral. Thats not hard, it just takes some awareness that it is needed, or so it would appear. I also understand that some care may be needed when switching modes, to avoid false data or other undesired artifacts.
Given that caveat, are there any other impediments or gotchas that I might be overlooking that might come with mixing SPI and async on the same bus? Has anyone tried to do this?