XOSC clock source for SAMD targets

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Hello all, 

Iam trying to configure the XOSC clock source, but the output clock from it seems to not increase than 32KHZ 

so what is the use of the GAIN bit in this register, how can i change the clock according the GAIN bit?

This is the code that i use to output a 32khz


  SYSCTRL->XOSC.bit.STARTUP = CSTSAMD_u8MCTRL_XOSC_STUPT;
  /*@Comment: to enable the XOSC as a crystal oscillator*/
  SYSCTRL->XOSC.bit.XTALEN =1;
  /*@Comment: Only run in IDLE sleep modes if requested
    by a peripheral. Disabled in STANDBY sleep mode. */

  SYSCTRL->XOSC.bit.RUNSTDBY = 0;
  SYSCTRL->XOSC.bit.ONDEMAND = 1;
  SYSCTRL->XOSC.bit.ENABLE = 1;
  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_XOSCRDY))
  {
    /* Wait for oscillator stabilization */
  }
  
  SYSCTRL->XOSC.bit.GAIN = CSTSAMD_u8MCTRL_XOSC_GAIN;


  

 

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For 32kHz you should use XOSC32K. GAIN is not for changing the frequency, it is there to adapt to the crystal you have.

Once you have a working oscillator (could even be one of the internal oscillators) you can use the DFLL to get 48MHz and the DPLL to get 48-96MHz (and then suitably divided you basically get whatever frequency you need out of a generic clock generator).

/Lars

 

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Is there a tolerance in the output frequency fom DPLL or DFLL, due to hardware limitations, maybe?

I use Oscillator XOSC32K as a reference clock for DPLL , but the XOSC32K generates 32.768KHZ according to the datasheet and i tested it as well, so the generated clock from DPLL is not always accurate, which confuses me. 

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Check "Oscillators Characteristics" (it's in the "Electrical Characteristics" section), it could be you get what can be expected.

/Lars

 

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Some time ago I measured the stability of the 48Mhz clock when the DPLL reference frequency is derived from a quarz. Over a one second period it's about 5ppm See DPLL

/Jerry

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Hello Jerry, 

How can i check that the PLL has stabilized, is there a bit in a register that can detect that, i can find any bit responsible about the stability in all PLL registers

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Nada awad wrote:

How can i check that the PLL has stabilized, is there a bit in a register that can detect that, i can find any bit responsible about the stability in all PLL registers

 

  while(!SYSCTRL->PCLKSR.bit.DFLLRDY)  /* Wait for DFLL ready */
    ;
  while(!SYSCTRL->PCLKSR.bit.DFLLLCKF)  /* Wait for DFLL fine lock */
    ;

 

This is copied from the code for a SAMD21J, See also the datasheet section 17.6.7

/Jerry

 

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How can i get ride of the jitter effect that occurs in the generated signal?

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Sorry for the late reply, was too busy over Christmas

One can't get rid of the jitter when the CPU clock is generated using the DPLL - that's an inherent property of phase locked loops. If you can tolerate using a lower CPU frequency you could use up to a 32MHz quarz oscillator at XIN (SAMD21)

What requirements do you have for the frequency stability?

Jerry

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Hello Jerry,

Never mind and happy new year ^^. I donot have  specific requirements for the PLL stability , i just want to make sure that the output frequency is correct with this error or jitter.

If it makes sense to have this jitter in the signal then i can be satisfied with the output frequency. =D 

 

/Nada

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Hello Nada,

   The measurements of the GPS PPS period in CPU clock periods showed that the frequency was nearly constant with an RMS error of about 7ppm over a second. It would be interesting to study the stability over shorter periods. If the division factor for the PLL changed the error would be about 700ppm

 

Jerry