SAML21 clock configuration

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I am trying set up SAML21 to run 48MHz clock.  Attached screen shot has my configuration.

 

XOSC (12MHz) -> GCLK1 (1.5MHz) -> FDPLL (48MHz) -> GCLK0 (48MHz) -> CPU

 

But the clock fails to initialize with this config. If  i change the clock divider on Generic clock generator 0 and bring down the frequency to 24 MHz it works well.

For that matter it works with anything below 24MHz.

 

System performance level is set to 2 , to operate in PL2 mode.

 

Could some one help with this.

 

 

 

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NVM wait states? The setting is in MCLK in atmel start.

/Lars

 

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Spot on. Thank you. A non-zero value for CONF_NVM_WAIT_STATE fixes it.