Hi there I am trying to interface the E70 with the AD5290 DAC by updating all 16 channels at regular intervals.
The serial protocol for this chip requires a total of 24 bits to be sent in each transfer to update one channel (i.e. NPCS must rise every 24 clock cycles). Therefore, what I want the DMA to do is send 24 bit packets 16 times to the chip without processor intervention.
I see in section 184.108.40.206 of the data sheet (Peripheral Deselection with DMA) that CSAAT and LASTXFER must be used with DMA. But if I am doing this every other transfer (e.g. breaking the 24 bit transfer into two 12 bit transfers) this will require a lot of processor intervention, which defeats the purpose of the DMA. I am totally confused about what is being presented in Figure 41-11, so not sure if the answer is in there somewhere.