I'm trying to implement a I2C master using the attiny85's USIC.
The datasheet is confusing regarding some aspects.
1)What makes the counter increase:USICLK or USITC (both bits are in USICR)?
2)Can i pull SDA low from PORTB even tho it's controlled by the output latch from USIDR?
3)I see that i can clock the thing from Timer 0 compare match? What register/channel from Timer 0? (OCR0A or OCR0B or both)
4)If i toggle only the USITC bit i assume the data won't be shifted from the USIDR,only the SCL line will transition from whatever state i left it in.USIDR shiftout should be done with USICLK...
5)I read the if i enable the 2 wire mode if i have the DDRB bits set to 1 and i write one to PORTB's corresponding bits i wont drive the line ,just release it and i can pull it down by writing 0 to PORTB's bits?
6)If i want to receive i basically set the DDRB bit for SDA to 0 thus making it an input and i'll find the data in USIDR? (Since if i want to output i just make DDRB to 1 and i output the data from USIDR )
Thx in advance :)