The target platform related to this question will probably be a 4808/9 but that MIGHT not be significant.
I've done some searching on the 'net and most of what I've found seems to be targeted at PLDs and such but what I would like to do is constrained by MCU clocks, timer prescalers, and counters that rarely have an up/down option (except for "phase correct" modes which seem to be absent from AVR-0 devices).
Here is what I would like to do:
1. I have a 1 second tick from an internal real-time clock counter OR a 1 second period square-wave from an external RTC.
2. I would like to generate 100ms (10Hz) events that are phase-locked to the 1 second period tick/square-wave.
3. I am guessing that I need a timer with variable TOP to generate the 100ms event rate and that the 100ms clock needs to be counted down by 10 to make a 1 second signal that can be phase-compared to the given 1 second signal. So, it sounds like we are already occupying two timer/counters for this (in addition to the internal RTC counter which is occupied, whether in use or not). Maybe the divide by 10 is at a slow enough rate that it can be done in software?
With this as a starting point, I am a bit puzzled about how to proceed. I am guessing that rates are slow enough that the phase comparison and the integration for the loop filter can be implemented totally in software. Does anyone have any ideas or suggestions for an algorithm that might work? For example, do I really need to implement a phase/frequency control loop to improve the initial lock speed? How would the phase comparison work?
Thanks for your suggestions and ideas!