Writing to Port Data Register with alternate pin function (Atmega328P)

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Hi,

 

I would like to know if I can write data to a port data register (for ex. PORTB) when some of the PORTB pins are used as an alternate pin function. On my development board (Atmega328P) pin 6 and 7 (XTAL 1 and XTAL 2) of PORTB are used for an external XTAL. I looked in the complete datasheet from the Atmega328P but wasn't sure if the information that I found answers my question. It looks like the answer can be found in table 14-4 on page 84 "Overriding Signals fo Alternate Functions".

 

My reasoning is that DDOE (Data Direction Override Enable) somehow is set when a clock is selected with the fuse bits. Then when DDOE is set, the output driver is disabled by DDOV (which is zero in all cases for PB7 and PB6 according to table 14-4). Is my reasoning correct? If yes then how DDOE is set (1)?

 

Thanks

 

 

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I'm not entirely sure I understand your question, but yes you can write to a port register, but any pin that is being used by an alternate function will ignore the write, at least as long as the pin is controlled by the alternate function.  For pins controlled by an Alternate use, the data latch for that pin will hold what ever is written to it, but it's output is not active while the alternate function is in use, but if it the alternate function is disabled, then the pin will now be under the control of the DDR and if an output, then also the data latch for the port pin.

 

Jim

 

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I'll agree with Kansas Jim on a couple points.  First is understanding the question...what in particular might bother you about internal signals being overridden?

 

And I agree with "alternate function taking over the pin".  Mostly.  I think you may need to be more specific about which function for a full discussion of possible exceptions.

 

You can put lipstick on a pig, but it is still a pig.

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I can see a concern about writing to a whole port rather than a single bit, and wondering what will happen to those alternate functions that happen to be set up on that port. Glitch? Change? 

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Thanks for the answers. My question is if it is possible to write to PORTB (for ex. PORTB = 0xFF) when pin 6 and 7 of PORTB are being used for a XTAL. It seems from your answers that it is possible, but I would like to be able to verify this by myself from the datasheet.

 

ki0bk wrote:

For pins controlled by an Alternate use, the data latch for that pin will hold what ever is written to it, but it's output is not active while the alternate function is in use, but if it the alternate function is disabled, then the pin will now be under the control of the DDR and if an output, then also the data latch for the port pin.

 

Jim

 

 

How can I verify from the datasheet that the output is disabled when a pin is used in an alternate function?

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Farad22 wrote:
Thanks for the answers. My question is if it is possible to write to PORTB (for ex. PORTB = 0xFF) when pin 6 and 7 of PORTB are being used for a XTAL.
When the CKSEl fuses are set to enable external clocks then the PB6/PB7 bits are completely isolated from the DDRB/PORTB/PINB registers. It won't matter what you write in bits 6 and 7 - they have no affect on the clock system.

 

Similarly if you were to enable SPI (SPEN in SPCR) then the SPI peripheral takes control of pins PB5/PB4/PB3 (but not PB2) so what you then do to those bits in PORTB/DDRB/PINB has no affect on the external pins either.

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Farad22 wrote:
My question is if it is possible to write to PORTB (for ex. PORTB = 0xFF) when pin 6 and 7 of PORTB are being used for a XTAL.

Yes.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Farad22 wrote:
How can I verify from the datasheet that the output is disabled when a pin is used in an alternate function?

 

As I mentioned, in general, yes.  But what do you define as "alternate function"?  ICP is an alternate function, but

ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.

Contrast with your question on XTAL1/2

 When used as a clock pin, the pin can not be used as an I/O pin.

But indeed,  shouldn't PVOE (and PVOV) be set in

 

 

 

[edit] Maybe it doesn't show up in the table because a fuse setting isn't the same as e.g. enabling SPI or USART?

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Thu. Nov 21, 2019 - 01:30 PM
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theusch wrote:

 

But indeed,  shouldn't PVOE (and PVOV) be set in

 

[edit] Maybe it doesn't show up in the table because a fuse setting isn't the same as e.g. enabling SPI or USART?

 

 

It looks like the output driver on PB7 is either controlled by DDRB register if DDOE is cleared. If DDOE is set it is controlled by DDOV (Table 14-2) Because DDOV is zero for each alternate function for PB7, it means that the output driver is disabled if DDOE is set. DDOE is set when the following condition (green box highlighted) is true/1 . It becomes true when INTRC AND EXTCK are both zero OR when AS2 is one. I cannot find under which condition INTRC AND EXTCK will be both zero. AS2 is easy to see as this is a bit that is set in ASSR register.

 

How can INTRC AND EXTCK both become zero so that the condition (green box) is true and therefore the output driver is disabled?

 

 

Last Edited: Thu. Nov 21, 2019 - 03:17 PM
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This is all very fine navel fluff inspection but does it really affect the price of rice in China?

 

Inspection shows that it IS the case that when bits in a PORT are controlled by a peripheral they are no longer affected by GPIO activity.

 

Sure the datasheets may have omissions/errors (they are actually rather famous for this) but surely what matters is what the chip is actually found to do?

 

(of course one should arrange to have their technical author summarily executed at a later date :)

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Farad22 wrote:
It looks like the output driver on PB7 is either controlled by DDRB register if DDOE is cleared. If DDOE is set it is controlled by DDOV (Table 14-2) Because DDOV is zero for each alternate function for PB7, it means that the output driver is disabled if DDOE is set. DDOE is set when the following condition (green box highlighted) is true/1 . It becomes true when INTRC AND EXTCK are both zero OR when AS2 is one. I cannot find under which condition INTRC AND EXTCK will be both zero.

I'm not sure what this goose chase is all about, it would be plainly obvious if the xtal[1,2] pins did not work when selected as the clock source and the chip would be bricked if an IO operation could set the pin state!!!

Second, seldom does the datasheet explain every internal operation of the chip, that would be giving away IP, but it would be expected for it to explain how to use each feature.

I for one like how Atmel details how the ports work and also shows (a typical) port schematic which explains how normal and alternate functions work, but would not expect them to detail every last internal operation.

Again why does any of this matter to you?

 

Jim

 

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I was under the impression that pin hardware functionality could be easily verified by the datasheet. I'm just learning more about Atemga 328P and how to read the datasheet after starting with my development board. I just wanted to verify what anyone else was saying ;) Apparently the datasheet only goes to a certain level of detail (because of IP). Thanks for the discussion.

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To summarize the relevant parts of the datasheet:

When using XTAL1/2, DDB6/7 are forced to 0, i.e input.

Writing to PORTB will assign its bits 6/7.

Those bits will not affect pins B6/7,

but they are readable.

 

Note that port b would still be usable

even if DDRB6/7 were not forced to zeros.

They start at zero and a careful programmer

will never set them to anything else.

 

It seems to me that OP was simply trying to avoid

relying something that was not in the datasheet.

Now that OP understands what is in the datasheet,

OP should be happy.

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