We ran into a problem with the clock calibration values.
When setting the FUSE_OSCLOCK bit in the OSCCFG fuse byte, the value in OSC20MCALIBA after reset is always set to 0x40, which leads to the actual master clock set far too high to 20MHz + 20%.
The LOCK bit in OSC20MCALIBA is set correctly. The LOCK bit seems to appear also in the register MCLKLOCK, here as R/W.
If we omit the FUSE_OSCLOCK bit, then we see a sensible value in OSC20MCALIBA, and the master clock is within its datasheet limits.
We are using ATMEL Studio V7.0.2389 with avr-gcc, device pack version 1.3.229
Not sure if this is an issue with the studio or an ATtiny1607 hardware bug.
Can somebody confirm this behaviour?