ATTiny1607 Clock Calibration Issue

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Hello All,

 

We ran into a problem with the clock calibration values.
When setting the FUSE_OSCLOCK bit in the OSCCFG fuse byte, the value in OSC20MCALIBA after reset is always set to 0x40, which leads to the actual master clock set far too high to 20MHz + 20%.
The LOCK bit in OSC20MCALIBA is set correctly. The LOCK bit seems to appear also in the register MCLKLOCK, here as R/W.
If we omit the FUSE_OSCLOCK bit, then we see a sensible value in OSC20MCALIBA, and the master clock is within its datasheet limits.
We are using ATMEL Studio V7.0.2389 with avr-gcc, device pack version 1.3.229
Not sure if this is an issue with the studio or an ATtiny1607 hardware bug.
Can somebody confirm this behaviour?

 

 

 

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It does the same thing on a mega4809- lock is on -> OSC20MCALIBA.CAL20M = 0x40

 

MCLKLOCK.LOCKEN is not loaded from the OSCLOCK fuse bit contrary to the register description (datasheet author reading their notes wrong)

 

MCLKLOCK.LOCKEN = 1 = also blocks calibration registers, bit is set only and is user set (not fuses)

OSC20MCALIBB.LOCK = 1 = bad value loaded into OSC20MCALIBA.CAL20M (fuses set)

 

I guess you just use LOCKEN when you have everything setup, as it doesn't seem you can lock the calibration bits separately as of now.

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Thanks for your answer. It confirms our findings. So this seems to be a hw bug of some ATtinys.

As a workaround, we will set LOCKEN right after clock setup.

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Total votes: 2

I've forwarded the issue.
Thanks.

 

-JE