AVR Freaks

I don't know if you are still searching for Initializing the clock at 120 MHZ but here my code to do it.  I made a LOOOOOT  of work and research to be able to clock it at this speed.  There is so many registers to configure, that's insane.  This is clocked from Internal.   There is some commented code, you can experiment with.  Good Luck!

Cedric

void ClockInitInt(void)
{
	//uint32_t PLLRATIO=4060;	//3730;  //122.776 MHZ
	uint32_t PLLRATIO=4061;	//3730;  //122.776 MHZ

	//Initialisation for 120 MHz (Or any speed you want, this code is set to 120 MHz) from the internal 32KHz Oscillator.

	// CONFIGURE FLASH MEMORY WAIT STATES
//	NVMCTRL->CTRLA.bit.RWS = 6; // 4WS allows up to 119 MHz, 5WS allows 120 MHz
	NVMCTRL->CTRLA.bit.RWS = 4; // 4WS allows up to 119 MHz, 5WS allows 120 MHz
	NVMCTRL->CTRLA.bit.AUTOWS = 0; // automatically determine the necessary wait states

//	NVMCTRL->CTRLA.bit.CACHEDIS0 = 1; // cache
//	NVMCTRL->CTRLA.bit.CACHEDIS1 = 1; // cache

	CMCC->CTRL.bit.CEN=0;			//Cache Disable //1=Enabled

	// CONFIGURE EXTERNAL 32K CRYSTAL OSCILLATOR
//	OSC32KCTRL->XOSC32K.bit.CGM = 1; // control gain mode: 1 = standard/XT 2 = high-speed/HS
//	OSC32KCTRL->XOSC32K.bit.STARTUP = 0; // oscillator startup time, 0 = 62 ms
//	OSC32KCTRL->XOSC32K.bit.ONDEMAND = 0; // always run
//	OSC32KCTRL->XOSC32K.bit.XTALEN = 1; // enable crystal driver circuit for XIN32/XOUT32 pins
//	OSC32KCTRL->XOSC32K.bit.EN32K = 1; // enable the 32 kHz output clock
//	OSC32KCTRL->XOSC32K.bit.ENABLE = 1;
//	while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY); // wait until crystal oscillator is stable and ready to be used as a clock source
//	OSC32KCTRL->RTCCTRL.bit.RTCSEL = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val; // RTC should use the external 32K crystal

	// CONFIGURE MASTER CLOCK
	MCLK->CPUDIV.bit.DIV = 1; // use a divisor of 1 for the master clock

	//Configure ClockGen1 for PLL INTERNAL
	GCLK->GENCTRL[1].bit.SRC=4;     //Internal 32KHz Oscillator.
	GCLK->GENCTRL[1].bit.DIV = 1; // divisor 1 for the input clock from the PLL
	GCLK->GENCTRL[1].bit.GENEN = 1;

	GCLK->PCHCTRL[1].bit.GEN = 1;  //PERIPHERAL 1
	GCLK->PCHCTRL[1].bit.CHEN = 1;  //ENABLE CHANNEL

	// CONFIGURE PLL0
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK= 0; // use GCLK as the PLL reference clock
	OSCCTRL->Dpll[0].DPLLRATIO.reg = (3<<16) + PLLRATIO;  //3661; //3455; //113.273 MHZ.  multiply OSC32K by 3662.11 to get 120 MHz (actual multiplier is LDR + 1 + LDRFRAC/32)  3661
	//OSCCTRL->Dpll[0].DPLLRATIO.reg = (3<<16) + 1464; // multiply OSC32K by 1464 to get 48 MHz (actual multiplier is LDR + 1 + LDRFRAC/32)  1464

	// errata: When using a low-frequency input clock on FDPLLn, several FDPLL unlocks may occur while the output
	// frequency is stable. Workaround: when using a low-frequency input clock on FDPLLn, enable the lock bypass
	// feature to avoid FDPLL unlocks.
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.LBYPASS = 1; // CLK_DPLL0 output clock is always on, and not dependent on frequency lock
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0; // always run
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = 1;

	while (!OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK) ; // no point in checking DPLLSTATUS.bit.CLKRDY, because LBYPASS is enabled

	// CONFIGURE CLOCK GENERATOR 0
	GCLK->GENCTRL[0].bit.SRC = 7; // use PLL0 as the input
	GCLK->GENCTRL[0].bit.DIV = 1; // divisor 1 for the input clock from the PLL
	GCLK->GENCTRL[0].bit.GENEN = 1;

	// do peripheral clock initialization here...
}