MCU ADC input when MCU powered down

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Morning,

 

I have an external battery which is permanently connected to my device. I have a basic A/D circuit to read the voltage of the battery (current limiting resistor with some polarity and over-voltage protection diodes), which connects to a spare A/D input on my MCU. At the moment, this circuit is permanently connected to the battery, whereas the MCU is only powered on when the device is switched on. As such, the input on the MCU A/D is much greater than the MCU VCC (which is effectively zero), and hence in violation of the datasheet maximum specification. Similarly, it'd be great if the MCU A/D input was high/infinite impedance in powered down state, but it's safe to assume this isn't the case.

 

What's the most logical approach to this scenario? Ideally I'd be able to 'turn on' the A/D circuit when the MCU is powered, and turn it off again when it's powered down.

 

Thanks!

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You could use high ohms to the adc pin & cross your fingers---let the unpowered side just pull everything down...bad:

   --it might still cause some damage or long-term effects

   --will keep draining the battery

   --high ohms will give a poor reading when you want it to work.

 

You could add a schottky diode (between pin & power) to help pull the pin down when power falls.

---still a constant power hog.

 

Better to run the Vbatt through a Pfet that feeding a lower ohms divider to the adc pin.

When the Pfet is off, then no power flows & essentially no battery drain.

The processor can momentarily turn on the Pfet to allow the Vbat to head to the divider & to the ADC pin. 

 

An easier way is to run the Vbatt through, say 10k, to an Nfet.  The Nfet  has a source resistor, say 1000 ohms to gnd.  The voltage there is the scaled measured voltage, say 1V max when Vbatt=10V.  The voltage only appears when the Nfet is on.  The gate control voltage, simply driven by an I/O pin, must be a few volts higher than this measured voltage to turn on the Nfet (Vgs>3V typ)---so better for a 5V system.  Use an Nfet rated a few hundred milliohm for a good result (the divider is then 1000.2/10100.2) & Vds rated greater than Vbatt to allow Vbatt blocking.

 

 

 

 

 

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. Jun 23, 2019 - 11:50 PM
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Thanks for that avrcandies, a FET certainly seems like the way to go.

 

This is a 3V3 system, so I'll have to do some calculations as to the correct NFET given the VBatt range.

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I came across this solution on a similar post, does this look ok? I would obviously vary the output voltage divider to suit, I'm more interested in the NFET-PFET combination.

 

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Yeah, that works good.  Or good enough, neglecting some microamps of leakage in the off state via Q3 & Q2...but in most cases the battery is not super small & you don't need a shelf life of 5 years.  So let the boat leak a few drips.

 

Keep the fets off while not taking measurements, to minimize power waste (if need be) from the resistors.

 

As mentioned, you can do it with just one fet (placed on top of R8, between R7 & ADC), if you are clever in divvying up  the 3.3V between turning on a fet (usually takes several volts)

& the adc voltage. But signal strength fets are a dime a dozen these days, so using two is no big deal.  

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Mon. Jun 24, 2019 - 03:13 AM
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Brilliant, thanks again for your help. The battery in question is indeed a fairly sizeable lead-acid, I'm really not worried about microamps of leakage at this point.

 

I'll give this approach a go.

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Make R1 100 ohms (or get rid of it) & add a 10k pulldown to the gate of Q3  (by the way, where is Q1??)

The 10K forces Q3 off when the AVR pin is not driving to any voltage or gnd level.

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Thanks for that, I had figured a pull down would make sense to avoid floating. As for Q1 I'm not sure, as mentioned above I've borrowed this schematic from a StackOverflow post :D

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avrcandies wrote:
So let the boat leak a few drips.
few means for a jellybean FET 100nA max at room temperature to 100microA max at max elevated temperature; bipolar transistors are usually an order of magnitude less leakage other than for for superBeta and low VCEsat transistors.

There are atypical FET that reduce IDSS.

 

BSS84L: Single P-Channel Logic Level Power MOSFET -50 V, -130mA, 10Ω

 

"Dare to be naïve." - Buckminster Fuller

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bipolar transistors are usually an order of magnitude less leakage other than for for superBeta and low VCEsat transisto

Thanks, I was wondering about that, but getting too lazy to look it up...might be good for long-term.  More current (base) short term, but only needs on for a moment to take a reading.

Yeah, a lot of these cmos ckts start out great, but not so great if you climb to under-hood temperatures.

I liked the old metal-gate cmos,,,,super super low quiescent (at low temps).

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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I was implementing the above design in my schematics last night, and realised I've actually got another similar circuit which will need some attention.

 

I have a RTC IC which is also permanently connected to the external battery (via a 3V3 regulator), for keeping time when the device itself is turned off, which communicates with the MCU via I2C. Below is the basic setup, where VBatt_3V3 is the permanent 3V3 rail and 3V3_SW is the switched 3V3 rail (only powered when the device is turned on).

 

 

Per my earlier issue, I can't have the SDA and SCL lines pulled high to VBatt_3V3 while the MCU is switched off. Similarly, if I instead use 3V3_SW as the pull up rail for the I2C resistors, the RTC IC I2C inputs will be floating while the MCU is powered down, where they need to be pulled high in an idle state. Bearing in mind that the MCU is the master, should the pull up resistors be to 3V3_SW regardless?

 

Would a similar N/P-FET arrangement be required here, whereby the RTC IC I2C inputs can remain pulled high when the MCU is powered off, but the I2C lines to the MCU are pulled low until the MCU is powered on? Or can I ignore all that, pull the resistors up to 3V3_SW and just leave the I2C lines floating to the RTC IC?

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permanently connected to the external battery (via a 3V3 regulator),

bad...constant power loss...use a micropower regulator, or coin cell for the RTC. 

 

I instead use 3V3_SW as the pull up rail for the I2C resistors, the RTC IC I2C inputs will be floating while the MCU is powered down

That's prob fine...add some 50k pull downs so they arern't  tumbling all over. 

 

Why not just keep both chips powered & let the AVR sleep?   Switches incur losses & make issues, as you see.

 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Thanks again for your input, it's greatly appreciated.

 

I should have been more specific; I am using a micropower regulator for the VBatt_3V3 rail, so power loss should be minimal.

 

I'll add the 50K pull downs and see how it goes, that certainly makes sense to me. The device can be turned off for several days (if not weeks) at a time, so it's definitely preferred to be able to turn all but the RTC off; I'm open to alternative approaches but would prefer this implementation in the first instance if possible.

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I'll add the 50K pull downs

Actually looking again, if the I2C resistors are on 3.3V _sw, if you are sure 3.3_SW falls all way to gnd then the I2C resistors (typical a few K) , will follow 3.3V_SW to gnd.  The I2C chip will not try to pull them high (open collector).  You just need to ensure that the 3.3V sw is  kept low.  Of course,the 50'ks do help in that regards.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!