SAMD20 DFLL differences between devices

Go To Last Post
2 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hello everyone,

 

I'm using the SamD20j18 and using the ASF DFLL to run on 48Mhz. Strangely enough i'm having problems with the same configuration on two different devices.

To start I had a configuration working on several devices. But when testing more I came across a device that did seem to have problems with this configuration. This device does run for a few seconds before hitting a reset/watchdog. In rare cases (5% of the time) it would run just fine, and all timings are good.

The first configuration worked on multiple devices but not on the newest one. This configuration does use the internal 32768Hz clock as reference,
Configuration 2 works on all devices and uses the internal 8MHz clock prescaled by 250 to create a 32000Hz reference clock.
Configuration 3 works on all devices and uses the 32Khz clock again, but this time prescales it to 1024Hz.

 

Configuration 1

/* DFLL closed loop mode configuration */
#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_5
#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32768)
#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)

/* Configure GCLK generator 5 */
#  define CONF_CLOCK_GCLK_5_ENABLE                true
#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
#  define CONF_CLOCK_GCLK_5_PRESCALER             1
#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false

 

Configuration 2

/* DFLL closed loop mode configuration */
#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_5
#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 32000)
#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)

/* Configure GCLK generator 5 */
#  define CONF_CLOCK_GCLK_5_ENABLE                true
#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC8M
#  define CONF_CLOCK_GCLK_5_PRESCALER             250
#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false

 

Configuration 3

/* DFLL closed loop mode configuration */
#  define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR   GCLK_GENERATOR_5
#  define CONF_CLOCK_DFLL_MULTIPLY_FACTOR         (48000000 / 1024)
#  define CONF_CLOCK_DFLL_QUICK_LOCK              true
#  define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK   true
#  define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP     true
#  define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE      true
#  define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE    (0x1f / 4)
#  define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE      (0xff / 4)

/* Configure GCLK generator 5 */
#  define CONF_CLOCK_GCLK_5_ENABLE                true
#  define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY        false
#  define CONF_CLOCK_GCLK_5_CLOCK_SOURCE          SYSTEM_CLOCK_SOURCE_OSC32K
#  define CONF_CLOCK_GCLK_5_PRESCALER             32
#  define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE         false

 

I cannot really find any big difference for the DFLL between these configurations except that the first configuration doesn't have a nicely round multiply factor(1464,84).

 

Does anyone have any clue why the first doesn't work on this device? And is there a risk in changing the software for all devices to one of the two other configurations?

 

Greetings,
Taxara

This topic has a solution.
Last Edited: Wed. Jun 19, 2019 - 09:48 AM
This reply has been marked as the solution. 
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi all,

 

After days in the datasheet I've found some answers.

 

The internal oscillators are quite inaccurate and might differ much on different devices. In my case the 32kHz internal oscillator on this particular device was 500Hz off and had a lot of drift (200Hz).

When using the dift compensation (which by default it does) it is forbidden to use an internal oscillator.  See  16.6.7.1 drift compensation. 

 

Since I only have access to a 16MHz crystal I used this one with a prescaler of 500 to create a 32kHz reference clock ( 35.1kHz is max frequency for DFLL input see Table 32-7. Maximum Peripheral Clock Frequencies ). 

make sure you take a look on how many prescaling bits are available, on SAMD20 only generic clock 1 has enough bits to do a prescaling as large as 500.

 

When I now output my core frequency using the next pieces of code:

Main

  struct system_pinmux_config config_pinmux;
  system_pinmux_get_config_defaults(&config_pinmux);
  config_pinmux.mux_position = MUX_PA28H_GCLK_IO0;
  config_pinmux.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT;
  system_pinmux_pin_set_config(PIN_PA28H_GCLK_IO0, &config_pinmux);

Conf_clocks

#  define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE         true

I have a steady 48Mhz clock.

 

I noticed that a lot of examples/people do use the internal rc oscilator with drift compensation. Keep in mind that with some devices this might fail.

Good luck to everyone who has to use the DFLL I hope I gave some useful information.

 

Greetings, 

Taxara