GCLK->GENCTRL and structure initialization

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To setup a generic clock generator one can do the following (for example set the external 32 kHz on generator 1):

    GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1));

Section 15.6.2.1 of the datasheet states that you must do the write in one 32 bit register write.  However, the following appears to work:

	GCLK->GENCTRL.bit.ID = 1;
	GCLK->GENCTRL.bit.SRC = GCLK_GENCTRL_SRC_XOSC32K_Val;
	GCLK->GENCTRL.bit.GENEN = true;

The question comes when I try to do the following:

GCLK->GENCTRL = (GCLK_GENCTRL_Type){{.ID=1, .SRC=GCLK_GENCTRL_SRC_XOSC32K_Val, .GENEN=true}};

I end up with a hung processor that I can't even program without doing a flash erase immediately after reset.  Looking at the ASF code, it will setup the register and then enable/disable GENCTRL in a separate command.  So I assumed it was because GENEN is not necessarily the last bit set, but setting it separately still seemed to cause the same issue.

 

What is interesting is that doing the structure initialization with GENDIV works fine:

GCLK->GENDIV = (GCLK_GENDIV_Type){{.ID=1, .DIV=1}};

Any insight on why the structure initialization version doesn't work with GENCTRL (I thought it might just optimize down to a single register write)?

 

Also, any insight on the single 32 bit write for GENDIV, GENCTRL, and CLCTRL.  Seems like something the datasheet says but doesn't get followed in actual code examples.

Last Edited: Wed. Jan 3, 2018 - 11:14 PM
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How about

	GCLK->GENCTRL.reg = (GCLK_GENCTRL_Type){{.ID=1, .SRC=GCLK_GENCTRL_SRC_XOSC32K_Val, .GENEN=true}}.reg;

/Lars

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Thanks Lars, 

That does work and the assembly comes out optimized down to just the address, very similar to the more traditional method.  Any insight on why gcc doesn't do the same thing without the .reg.  I had assumed it would.

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Hello Everyone (especially Lars ;) )

 

I have the same problem ( making GCLK work). Here is my code.

 

GCLK->GENCTRL[0].reg =

        GCLK_GENCTRL_DIV(1) |

        GCLK_GENCTRL_GENEN |

        GCLK_GENCTRL_SRC_XOSC0 ;

  GCLK->PCHCTRL[24].reg =

        GCLK_PCHCTRL_CHEN |

        GCLK_PCHCTRL_GEN_GCLK1;

GENCTRL[0].GENEN.bit=1

 MCLK->APBDMASK.bit.DAC_ = 1;

  DAC->CTRLA.bit.SWRST = 1;

 

For a short time, I can see the bytes of GCLK actually increase (meaning GCLK is moving forward)

 

 

 

 

 

, however, after a half-second, it stops incrementing and I am sad ;(. Please help me set this GCLK.

 

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I don't get it, nothing should be incrementing in the GENCTRL register so that is perfectly ok. Your are using GCLK_GENCTRL_SRC_XOSC0, is it configured ok? 

  GCLK->PCHCTRL[24].reg =
        GCLK_PCHCTRL_CHEN |
        GCLK_PCHCTRL_GEN_GCLK1;

And what about GCLK1, is it configured? I suggest you try first using GLCK0 and then don't even touch GCLK->GENCTRL[0].reg initially, GCLK0 has a working config after reset.

    MCLK->APBDMASK.bit.DAC_ = 1;
    DAC->CTRLA.bit.SWRST = 1;

24 is SERCOM3 but then you try to config the DAC?

/Lars

 

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Please don't PM.

I already mentioned it is strange you setup PCHCTRL channel 24 when you intend to use the DAC (it is channel 42). You can write it like this

	MCLK->APBDMASK.bit.DAC_= 1;
	GCLK->PCHCTRL[DAC_GCLK_ID].reg = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
	

and this needs to be done before you do anything with the DAC.

Also, setting GCLK0 to use XOSC can only work if XOSC has been setup. As mentioned you can skip this and try with the default GCLK0 first.

I found more example code by searching for DAC_GCLK_ID:

https://community.atmel.com/forum/samd51-metro-m4-adc-code-help

/Lars

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Many thanks Lars. I did not see your first message here and PMd you ( even though I ticked the option for "notify me when a reply is posted", I get no notification. And NO, it was not in my spam folder for email ;)), sorry if it bothered you!

 

Nothing to do with DAC! I only want to make USART work and then I read somewhere that maybe my clock is not running, and had to delve into GCLK. 

 

Regarding your point on XOSC0, you are right! I have no external clock and it seems my chip does not have a crystal for time! (based on my supervisor).

 

Anyhow I will read the webpage you shared and will try to solve this. BTW, my chip is SAMD51G19A and is builtin itsybitsy M4 express, which is inducing lots of pain to work on.

 

Thanks!