Having spent some time reading and rereading the datasheet, I've got a few questions for anyone in the know here!
I only need to access 64K of SRAM and don't want to use latches. I think that means "4-port" EBI mode "NOALE".
Q#1 - There seems to be an option of using a chip select or not using a chip select. I remember seeing this difference in some of the timing diagrams too. Would you still set up the ASIZE/BASEADDR even if the CTRLA MODE=00 (DISABLE)?
Q#2 - Any reason to use a chip select unless you have multiple memory devices? Is it a good idea to tie the SRAM /CE low and skip it or let the AVR generate it?
Q#3 - If ASIZE is smaller, does the EBI take over less address lines leaving them available for I/O ?
Q#4 - Does LPCMODE in CTRL not apply if you are not in "Low Pin Count Mode" - ther only options are ALE1 or ALE12. I would set SRMODE=11 (NOALE) and IFMODE=10 (4PORT).
Q#5 - If I set BASEADDR if set to 0x10000 would put the SRAM at 0x10000. I saw the __far_mem_read(addr) and __far_mem_write(addr, data) function access to the memory. Is there any gcc pointer access that is also workable?