AVR Freaks

So if I use 4 port mode and set EBIOUT to put A15:A8 on PORTF, but I only want to access 64K addresses (A15:A0), can A21:A16 be repurposed for other tasks?  What I am wondering is if the direction of these pins is set to input, not output, will the EBI control them?

Interesting, so does this mean that it uses the size window specified and knows which address pins are in use and which are not?  So the A21:A16 could be used for output or input?

I'm not following that diagram at all and I don't see any reference to it to explain it...

What is n-1 ?

We are talking about the baseaddr, but does that relate to the address pins it uses, or is it the address size that determines them?  Isn't there 4 ranges for that?  Does EBI's most significant address bit depend on all 4 ranges?

I wonder if it looks at all 4 ASIZE values to determine the highest EBI address pin, or if each one while being used sets the highest address pin.

Is it better to use CS0 or CS3?  The chart where it is redefining CS for address would suggest it might be better to start at CS3 and go downward.

Also:

The right-hand column shows that all four CS
lines are used as address lines when only CS3 is enabled.
Figure 27-

Why would all 4 be address lines if only CS3 is enabled?  Is CS3 not needed?  What becomes CS3 in this case?

Each ASIZE does have that range of values, but there is an ASIZE for CS0, an ASIZE for CS1, an ASIZE for CS2, and an ASIZE for CS3, correct?  If CS0 is set to "256 bytes" and CS1 is set to "65536" bytes then one uses 8 address lines and the other 16 address lines.  If both CS0 and CS1 are configured for use, how many address pins will the EBI use?  16 all the time?  Or 8 when accessing CS0 and 16 when accessing CS1?

I am completely lost.  If you have one memory device (one CS line), then CS0, right?  if you have two memory devices (two CS lines), why CS1 and CS2 instead of CS0 and CS1?

If you choose CS0, then is A16:A17 available for 18 bit memory?  Wouldn't it be better if you have one memory device to use CS2 for it leaving A16:A17 available?

Parts are finally in and I have the EBI working in 4 port mode with 16 address lines (64K).  I've got it working with the FRAM (150ns) and SRAM (55ns), but I can't get it to be solid and reliable with SRAM (10ns).  It will appear to work, but when I put it through a bunch of tests, it will fail.  Sometimes randomly, sometimes not randomly.  I've attached my code if anyone wants to look through it, but it works great with the FRAM and 55ns SRAM, but it is always possible there is a bug.

The sram_read/sram_write are just kludges to let my sram functions written with something else work without redirecting them to the __far_mem_read/write functions.

I put the 64K at 0x10000 using CS0 for now.

I tried slew rate limiting (I know there is a better way to set all pins at once), but it did not have an effect.

I added a ton of decoupling to the solderless breadboards, did seem to make things a little better, but the SRAM 10ns still fails.

I had a similar problem with some other ISSI 10ns memory with another AVR using its memory interface in the past.  Could it be that 10ns SRAM is just not going to work on a breadboard because of the capacitance or something?

I can see that the 10ns does indeed drive the i/o pins in around 10ns.  You can see some oddities in the sram_cell test where I am reading the byte twice, this was a mod to try to figure out what it was doing.  An error I was able to capture showed the write, and then the two reads.  Both reads should have been the same, but the first one the SRAM drove the line high when it should not have and the second one it look the line back low which was correct.  At this point there was no memory location in the memory that should have had that bit on - the cell test was transitioning it between two values and both values have this particular bit set the same.  So it shouldn't have mattered what any of the 16 address lines were doing, it should have been low the first time and the second time.

Maybe I should try to design a quick test board to get it off the solderless BB and see what it does there...

#include <avr/io.h>
#include "util/atomic.h"
#include <stdio.h>
#include "avr/pgmspace.h"

#include "cdelay.h"

#define sram_read(x) __far_mem_read(0x10000+x)
#define sram_write(x,y) __far_mem_write(0x10000+x,y)

#define __far_mem_read(addr)                            \
        (__extension__({                                \
    uint32_t temp32 = (uint32_t)(addr);     \
    uint8_t result;                         \
    asm volatile(                           \
      "in __tmp_reg__, %2"     "\n\t" \
      "out %2, %C1"            "\n\t" \
      "movw r30, %1"           "\n\t" \
      "ld %0, Z"               "\n\t" \
      "out %2, __tmp_reg__"    "\n\t" \
      : "=r" (result)                 \
      : "r" (temp32),                 \
        "I" (_SFR_IO_ADDR(RAMPZ))     \
      : "r30", "r31"                  \
    );                                      \
    result;                                 \
  }))

#define __far_mem_write(addr, data)                     \
        (__extension__({                                \
    uint32_t temp32 = (uint32_t)(addr);     \
    asm volatile(                           \
      "in __tmp_reg__, %1"     "\n\t" \
      "out %1, %C0"            "\n\t" \
      "movw r30, %0"           "\n\t" \
      "st Z, %2"               "\n\t" \
      "out %1, __tmp_reg__"           \
      :                               \
      : "r" (temp32),                 \
        "I" (_SFR_IO_ADDR(RAMPZ)),    \
        "r" ((uint8_t)data)           \
      : "r30", "r31"                  \
    );                                      \
  }))

char s1[128];

void uart_putc(uint8_t AByte)
  {
    //wait until ready
    while ((USARTD0_STATUS & USART_DREIF_bm)!=USART_DREIF_bm)
      ;

    //tx
    USARTD0_DATA=AByte;
  }

void uart_puts(char *AString)
  {
    uint8_t c1;

    for (c1=0;AString[c1];c1++)
      uart_putc(AString[c1]);
  }

void uart_puts_P(const char *AString)
  {
    uint8_t c1;

    for (c1=0;pgm_read_byte(AString+c1);c1++)
      uart_putc(pgm_read_byte(AString+c1));
  }

void dump(uint32_t AAddress, uint16_t ALines)
  {
    uint8_t c1,c2;
    uint32_t ui1;

    for (ui1=AAddress;;)
      {
        sprintf(s1,"%08lx: ",ui1);
        uart_puts(s1);

        for (c2=0;c2<16;c2++)
          {
            c1=__far_mem_read(ui1+c2);
            //c1=*(volatile uint8_t*)((ui1+c2) | _BV(15));

            sprintf(s1,"%02x ",c1);
            uart_puts(s1);
          }
        uart_puts("\n\r");

        ui1+=16;
        ALines--;
        if (ALines==0)
          break;
      }
  }

const char PROGMEM MSG_TESTING[]="Testing Static RAM";
const char PROGMEM MSG_DATATESTFAIL[]="\n\rData line test fail.\n\r";
const char PROGMEM MSG_ADDRTESTFAIL[]="\n\rAddress line test fail.\n\r";
const char PROGMEM MSG_LATCHTESTFAIL[]="\n\rLatch test fail.\n\r";
const char PROGMEM MSG_CELLTESTFAIL[]="\n\rCell test fail.\n\r";
const char PROGMEM crlf[]="\r\n";

void sram_datatest()
  {
    uint8_t c1,c2;

    //datatest
    for (c1=0,c2=1;c1<8;c1++)
      {
        sram_write(0,c2);
        sram_write(1,0x00);
        sram_write(2,0xff);
        if (sram_read(0)!=c2)
          {
            uart_puts_P(MSG_DATATESTFAIL);

            //halt
            for(;;)
              ;
          }
        c2<<=1;
      }
  }

void sram_addrtest()
  {
    uint8_t c1,c2;
    uint16_t ui1;

    //addrtest
    for (c1=0,c2=0xa3,ui1=1;c1<16;c1++)
      {
        sram_write(ui1,c2++);
        ui1<<=1;
      }

    //verify values

    //addrtest
    for (c1=0,c2=0xa3,ui1=1;c1<16;c1++)
      {
        if (sram_read(ui1)!=c2++)
          {
            fail:
            uart_puts_P(MSG_ADDRTESTFAIL);

            //halt
            for(;;)
              ;
          }
        ui1<<=1;
      }
  }

void sram_celltest()
  {
    uint16_t ui1;
    uint8_t c1,c2;

    uart_puts_P(MSG_TESTING);

    //pass 1 : fill with 0x55
    for(ui1=0x0000;;)
      {
        sram_write(ui1,0x55);
        ui1++;
        if (ui1==0)
          break;
      }
    uart_putc('.');

    //pass 2 : verify 0x55, fill with 0xaa (UP)
    for(ui1=0x0000;;)
      {
        c1=sram_read(ui1);
        c2=sram_read(ui1);

        if (c1!=0x55 || c1!=c2)
          {
            //fail:
            uart_puts_P(MSG_CELLTESTFAIL);
            sprintf(s1,"%08lx %02x!=55 (%02x/%02x/%02x) %02x",ui1+0x10000L,c1,sram_read(ui1),sram_read(ui1),sram_read(ui1),c2);
            uart_puts(s1);

            //halt
            for(;;)
              ;
          }
        sram_write(ui1,0xaa);

        ui1++;
        if (ui1==0)
          break;
      }
    uart_putc('.');

    //pass 3 : verify 0xaa, fill with 0x00 (DOWN)
    for(ui1=0xffff;;)
      {

        c1=sram_read(ui1);
        c2=sram_read(ui1);
        if (c1!=0xaa || c1!=c2)
          {
            uart_puts_P(MSG_CELLTESTFAIL);
            sprintf(s1,"%08lx %02x!=aa (%02x/%02x/%02x) %02x",ui1+0x10000L,c1,sram_read(ui1),sram_read(ui1),sram_read(ui1),c2);
            uart_puts(s1);

            //halt
            for(;;)
              ;
          }
        sram_write(ui1,0x00);

        ui1--;
        if (ui1==0xffff)
          break;

      }
    uart_putc('.');
    uart_puts_P(crlf);
  }

int main(void)
  {
    //disable wdt
    ATOMIC_BLOCK(ATOMIC_FORCEON)
      {
        CCP=CCP_IOREG_gc;
        WDT_CTRL=WDT_WCEN_bm;
      }

    //switch to external oscillator
    ATOMIC_BLOCK(ATOMIC_FORCEON)
      {
        //enable external oscillator
        CCP=CCP_IOREG_gc;
        OSC_CTRL|=OSC_XOSCEN_bm;

        //wait for it to be ready
        while (!(OSC_STATUS & OSC_XOSCRDY_bm))
          ;

        //switch to external oscillator
        CCP=CCP_IOREG_gc;
        CLK_CTRL=CLK_SCLKSEL_XOSC_gc;

        //wait until we are switched
        while ((CLK_CTRL & CLK_SCLKSEL_gm)!=CLK_SCLKSEL_XOSC_gc)
          ;

        //disable internal oscillator
        CCP=CCP_IOREG_gc;
        OSC_CTRL&=~OSC_RC2MEN_bm;

        //lock
        CCP=CCP_IOREG_gc;
        CLK_LOCK=CLK_LOCK_bm;
      }

    //configure usart (pd2 rxd, pd3 txd)
    PORTD_DIRSET=_BV(3);
    USARTD0_CTRLB=USART_RXEN_bm | USART_TXEN_bm;

    //2mhz 57600
    //USARTD0_BAUDCTRLA=150;
    //USARTD0_BAUDCTRLB=0b10010000;

    //57600 baud
    USARTD0_BAUDCTRLA=31;
    USARTD0_BAUDCTRLB=0;

    //115200 baud
    /*USARTD0_BAUDCTRLA=15;
    USARTD0_BAUDCTRLB=0;*/

    //110 baud
    /*USARTD0_BAUDCTRLA=130;
    USARTD0_BAUDCTRLB=112;*/

    //slew rate
    /*
    PORTH_PIN0CTRL=_BV(PORT_SRLEN_bm);
    PORTH_PIN1CTRL=_BV(PORT_SRLEN_bm);
    PORTH_PIN4CTRL=_BV(PORT_SRLEN_bm);

    PORTK_PIN0CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN1CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN2CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN3CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN4CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN5CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN6CTRL=_BV(PORT_SRLEN_bm);
    PORTK_PIN7CTRL=_BV(PORT_SRLEN_bm);

    PORTF_PIN0CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN1CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN2CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN3CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN4CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN5CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN6CTRL=_BV(PORT_SRLEN_bm);
    PORTF_PIN7CTRL=_BV(PORT_SRLEN_bm);

    PORTJ_PIN0CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN1CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN2CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN3CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN4CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN5CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN6CTRL=_BV(PORT_SRLEN_bm);
    PORTJ_PIN7CTRL=_BV(PORT_SRLEN_bm);
    */

    //configure EBI
    PORTH_DIRSET=_BV(0) | _BV(1) | _BV(4); //we, /re, /cs0
    PORTK_DIRSET=0xff; //a0-a7
    PORTF_DIRSET=0xff; //a8-a15

    EBI_CTRL=EBI_SRMODE_NOALE_gc | EBI_IFMODE_4PORT_gc;

    EBI_CS0_CTRLA=EBI_CS_ASPACE_64KB_gc | EBI_CS_MODE_SRAM_gc;
    EBI_CS0_CTRLB=EBI_CS_SRWS_1CLK_gc;
    EBI_CS0_BASEADDR=0x10000 >> 8;

    for(;;)
    {
    sram_datatest();
    sram_addrtest();
    sram_celltest();

    Delay_s(1);
    }

    __far_mem_write(0x10000,0x21);
    __far_mem_write(0x10001,0x43);
    __far_mem_write(0x1fffe,0x65);
    __far_mem_write(0x1ffff,0x87);

    for(;;)
      {
        dump(0x10000,4);
        dump(0x1ffc0,4);
        Delay_ms(1000);
      }

    //halt
    for(;;)
      ;
  }

Thanks; I bought it before the prices went up thankfully!

I'm going to hook up a scope and see what the signals look like with it next.

Connected the SRAM CS to ground so it would always be enabled - same result.  It may run a couple of passes, but then it will fail.

It is on a solderless breadboard right now with the small wire leads that have tiny pin connectors on the end.  Here is my question - if this were on a proper pcb, would it still be happening?  I'm surprised that going to the length of 7 wait cycles doesn't allow it plenty of time, but this is what I saw last time I messed with this (on another breadboard with another 10ns ISSI SRAM), it is giving the wrong results.

So - a question about avr1312 - why does the ebi_driver.h want you to :

         *  \note If interrupts are used, add the _far_mem_enter_ISR() and
         *        _far_mem_exit_ISR() in the interrupt routine to avoid reading
         *        or writing to the wrong location.


	#define _far_mem_enter_ISR()  uint8_t volatile saved_rampz = RAMPZ; \
                                      RAMPZ = 0;


	#define __far_mem_exit_ISR()   RAMPZ = saved_rampz;

Why should the ISR assume anything about RAMPZ?  Shouldn't it assume RAMPZ could be anything and that if it needs to do something involving RAMPZ, then it would save/set and restore it?  Or is this because gcc doesn't really know about RAMPZ?