from microprocessor to AVR to SRAM

Go To Last Post
11 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hello
Today I come or for those who will recognize my problem, I come back because I could not find a solution.
So for over 6 months I try to put in a microprocessor system a microcontroller between the processor and the SRAM. This not to build the capacity of the latter, but to be able to see and modify certain information.

For my solutions tested and without satisfactory result
At first, with the ATmega128 I got hooked on the address bus and the control bus, but the data bus crosses from one port to the other. Subsequently I made all the bus (address, data and control) by my Uc but this foid if I used an ATmega1280 but without success

I leave it to you

thank you

Tek-Tekel

Last Edited: Thu. Apr 18, 2019 - 12:42 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

But Tekel, lets be honest, lets suppose you are someone else...after reading your thread, could you come out with any valuable information ?

 

This forum is mostly engineers...SW and HW engineers....try to think this way and provide more "valuable" information...a schematic atleast.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

yes very little info.

 

I assume that you have done something like this :

 

so first which latch do you use ?

which speed of the AVR, RAM ?

Last Edited: Thu. Apr 18, 2019 - 09:40 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thank you for your answers
this configuration I discovered shortly and it is very useful to me. But it represents the second phase of my project because my first goal is to make sure my μc behaves like an SRAM in a microprocessor system.
thank you

Tek-Tekel

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Welcome, but we havent provided any answer.

 

@ sparrow2 : am completly lost though... ;-)

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Ok now I see understand the question, and my question is why? :)

 

For what you want to do it's normal to use dualport RAM.

 

There is a big problem with the AVR as a RAM, and that is speed! 

 

Unless you can make the micro make 10+ wait states. (or it has a hold signal)

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thanks already
My first schema was based on data processing speed and then my μc worked with a frequency of 16MHz and the microprocessor at 4MHz and so I just thought to take only the data bus completely and consult the bus. address and control like any other memory cell in the system.

I put my first schema

But already I can not recover the data that comes from the microprocessor. This is my first chalenge

 

Subsequently after more programming attempt, I penned that I had a problem of synchronization with the microprocessor so I made a second diagram that I put here

but my problem remains the same. That of being able to put a μc in the place of an SRAM in a microprocessor system.

you can help me and all the ideas are good
thank you

Tek-Tekel

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

in fact I would like to have access to the information stored there.
Without giving you a lesson you know that in such a system the results of operations are stored in the RAM so for me to be able to modify these data to enter a better system according to need.

For suggestion I did not understand
thank you

Tek-Tekel

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

You want to do something like his:
https://cdn.hackaday.io/files/7354314633536/ZAViouR%20v1.02.pdf

Having the avr appear as ram is not the most efficient solution. The z80 might do a read/write in 300ns. The avr at 16MHz would take 5 clocks - not enough to do the work required. You could slow the z80 down, but you might as well just have the avr emulate the z80. In the link i provided, the z80 is free to access the sramat full speed. When the avr wants to gain access, it asserts busrq and waits for the z80 to release the bus. The avr can then access the ram. When it is finished, it lets the z80 control the bus.

Here’s another variation on the theme:
https://cdn.hackaday.io/files/1599736844284832/A040618%20-%20SCH.pdf

Last Edited: Thu. Apr 18, 2019 - 12:13 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Instead of dualport RAM, you could look into a true share of the RAM.

 

I assume that the "real" RAM is fast (like 55ns), so if you do a sync with the AVR and the Z80 they should both be able to get the RAM 1/2 of the time. That was how many of the 1980's computers shared the RAM between CPU and Video.

 

For my C64 that is a 1MHz 6502 computer, the RAM setup was 2MHz 1/2 of the time the video had the RAM (and always made reads to refresh the DRAM). I had a CP/M module for it with a 4MHz Z80, and that had logic to control the clk, so 2 4MHz clk's, then the next 2 clk's was blocked to make sure that the video could make a read (so the Z80 hust have a pin to make the bus float), perhaps if you can find that diagram it could give some ideas (there was also a 4 bit adder involved you don't need)   

 

 

The diagram :

 

http://www.baltissen.org/images/...

 

info: Top left is the connector on the C64

DOT is a 8MHz (video) clk that keep everything in sync.

Last Edited: Thu. Apr 18, 2019 - 12:28 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

This is a repeat of this:

 

https://www.avrfreaks.net/forum/...

 

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

Topic locked