I2C pull up resistor location - Split from Weird signals on SDA/SCL pins for I2C

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jgmdesign wrote:
EDIT:  The resistors must also be at the last device on your bus.  Not at the microcontroller.

Hi Jim,

Is this really really important?  I have been putting the pullups on an EEPROM I am using, but have subsequently added more I2C devices.  I think some of them may not be in a line on the bus, but the SDA and ACL pairs run parallel from two different devices, with just one set of 4.7k pull ups.  I am going to have to be more careful in my creations moving forward.  I'm glad you mentioned that.  Another good day, starting out learning something new.

Last Edited: Fri. Apr 5, 2019 - 04:16 PM
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Yes it is important, especially when running at the higher speeds. With the resistors at the end of the bus, the entire length of each line are properly terminated.

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

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OK, thanks Jim.  Makes sense.  I will modify my designs accordingly.

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With pull-ups of a few hundred ohms or higher, you are not really terminating any transmission lines. Typically PC traces, ribbon cables, and such are in the range of 90 ohms to 150 ohms. Also, unless the channel distance is quite long, you never see the results of poor termination! Consider this:

 

1. For a circuit board, the propagation velocity is in the range of 1ns per foot. Extremes might be 0.8 to 1.2 ns/foot.

 

2. The reflection from an unterminated transmission line finds its way back at the sender in the time the signal takes to go to the far end, then return. So, for a 2 foot line, which is pretty long for a single board, the echo will come back in around 4ns.

 

3. On I2C/TWI with resistive pull-up and nominal trace capacitance, rise times can be 5-10ns. Fall times are a bit faster since it is an open-drain transistor pulling down instead of a resistor pulling up.

 

4. For that hypothetical 2 foot line, the echo will come back during the rise time, and will be swamped by the RC of the line. For a shorter line, the echo will come back even less time and will be lost in the very earliest of the rise. 

 

Now, if you have an unusually long line, you might be able to  see that  step from the open-end echo, but you would need a pretty fast scope to see it. 

 

This is quite different from, lets say, RS422/428 where the lines can be quite long. There terminating resistors (somewhere around 120 ohms as I recall) are very much in order. But, for I2C/TWI, its a whole different ball game. You CAN put those resistors anywhere on the line and in the very large proportion of cases, there will be virtually no consequence.

 

This is certainly NOT a problem in the OP's image in the first post. I would opt for missing scope probe ground connection, myself. The clock signal SHOULD be very close to 50% duty cycle.

 

Jim

 

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Thu. Apr 4, 2019 - 06:38 PM
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For a shorter line, the echo will come back even less time and will be lost in the very earliest of the rise. 

 

Interesting.

I would have expected to see the reflection within the ringing at the top of the transition, as the line is still experiencing a step voltage increase "in the very earliest of the rise".

 

JC 

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@KA7EHK/Jim

Far be it for me to ever question your experience, but are you saying that it does not matter where you put the pull up/termination resistors on an I2C bus?  We have had countless threads here on I2C and in pretty much every one its mentioned to make sure that the pull up/termination resistors are indeed at the end of the lines.  Even with resistors of several K-ohms, bus signal waveforms are very different when the resistors are not placed at the end of the bus lines.  This especially holds true as the I2C line speeds grow faster as they have in recent years.

 

East Coast Jim

 

EDIT:  I do agree that in the case of the OP there may be something else at play.

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

Last Edited: Thu. Apr 4, 2019 - 08:08 PM
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Think of what happens....

 

1) In logic low state, the output  transistor turns off and the voltage starts to rise. It rises with a time constant that is set by the capacitance of that network (mostly stray trace C) and the pull-up resistor.

 

2) That instant when the transistor turns off is a sharp transition. That propagates just a bit slower than the  speed of light (speed depends on the effective dielectric constant of the environment around the trace - mostly air and FR4 circuit board). 

 

3) That wave reaches the far end, and reflects since it is under-terminated. That is, the impedance at the end is higher than the characteristic impedance. Because the "termination" is higher than the characteristic impedance, the step will be upward.

 

4) The reflection then heads back toward the other end of the trace.

 

5) When it reaches the other end, the voltage has risen only maybe half of the way to its final value (in a normal I2C environment with ordinary GPIO transistors driving the line).

 

6) So, a scope with good sensitivity and bandwidth MIGHT see a small upwards "hitch" in the leading edge.

 

Now, if the rise time is faster (say 2-3ns), and the trace longer, you certainly could see it. But, for most limited bandwidth systems, it will appear as ringing rather than as discrete steps. You actually need a pretty clean system to see the individual reflection steps bouncing back and forth. Incidentally, you can see line reflections when the line is driven by normal logic that has rise and fall times of a few nanoseconds. Here, the drive impedance is low compared to the line impedance while the termination is high. Again, with a good scope, you can easily see the resulting reflection steps.

 

For normal speed I2C, it really makes little difference where you put the resistors. For the much newer fast speed and ultra fast speed, then you DO want to put it at the far end. Those systems are defined for smaller pull-up resistors that come much closer to a terminating resistance. Also, the clock speeds and the data bit times are much shorter, so that the data sampling time is pushed up, with much less delay between the clock edge and the sample edge. That, in itself, make the higher speed systems more susceptible to reflections. So, for those, you really should put the resistors at the far end. For normal speed, it makes no difference.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Thu. Apr 4, 2019 - 08:14 PM
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ka7ehk wrote:
Typically PC traces, ribbon cables, and such are in the range of 90 ohms to 150 ohms

I measured the resistance of one wire in a standard 2 foot long ribbon cable and got half an olm.  Not sure where you are getting your numbers.

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DC resistance is far different from the characteristic impedance. You measure DC resistance with an ohm meter. Characteristic impedance is measured with a network analyzer or by varying the load resistance to the point where there are no reflections. There are other methods, also.

 

Characteristic impedance is mostly a high frequency effect. That said, the NW-SW Power Intertie (from the Columbia River on the Oregon/Washington border to Los Angeles) is so long that it would have been several wavelengths at 60Hz. It would have been very difficult to deal with phasing between the Los Angeles power grid and intertie power. That is one of the big reasons for choosing a DC link.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Thu. Apr 4, 2019 - 08:21 PM
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I still disagree Jim, but too each his own.

Other Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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It looks like there is a bus-contention on the Data line.  The signal can't go below Vcc/2 when the Master is trying to pull it to Ground (0 volts).  Something else is holding the Data line high, or is trying to.    The SCL clock line doesn't look right either.  It would normally have clusters of nine positive-going pulses (8 data bits and an ACK bit).

 

Are you using a pre-written library for I2C?  Or are you bit-banging your code?   Does your processor have built-in peripheral registers that handle I2C in the background?  On AVRs, this is called the TWI section instead of I2C.

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Yes, it does look a lot like bus contention. That said, even this does not quite add up. It is like it has a hard time pulling low. THAT should happen only if there is some full logic output on the same line(s). Something that is capable of pulling hard high. 

 

So, it is time to ask the question: what is the real circuit of the bus? Everything that is connected to it. 

 

BUT, it is also important to ask: how is the 'scope connected? And, how about two traces, one with SCL and the other with SDA? On the same screen?

 

Remember, however, this is SMBUS and it is with a PIC,

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Fri. Apr 5, 2019 - 06:18 AM
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I wonder if it is self-contention? ie the OP hasn't configured SCL and SDA as open-drain outputs but as push-pull outputs?

#1 This forum helps those that help themselves

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#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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It should not make much difference where your pullups are physically placed.    I think that the countless threads here on I2C and in pretty much every one its mentioned are from jgmdesign

 

The pullup value and bus capacitance determine the risetime.    You should see a detectable risetime and very fast falltime to and from VCC.   At the limit it looks like a Shark's Fin.   Beyond the limit,   the SharkFin gets shorter as the risetime exceeds bus clock.

 

The AVR TWI peripheral has slew-rate limiting.  So it should be tolerant of sharp glitches.

 

I do not understand the scope trace in #1.

Personally,   I would display a short Logic Analyser sequence.   Display a single SharkFin on a scope if you are worried about the hardware levels.

 

Like Brian,   I suspect a push-pull contention.

 

Post the code.   Post the schematic.

 

David.

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ka7ehk wrote:

 

1) In logic low state, the output  transistor turns off and the voltage starts to rise. It rises with a time constant that is set by the capacitance of that network (mostly stray trace C) and the pull-up resistor.

 

2) That instant when the transistor turns off is a sharp transition. That propagates just a bit slower than the  speed of light (speed depends on the effective dielectric constant of the environment around the trace - mostly air and FR4 circuit board). 

 

3) That wave reaches the far end, and reflects since it is under-terminated. That is, the impedance at the end is higher than the characteristic impedance. Because the "termination" is higher than the characteristic impedance, the step will be upward.

 

4) The reflection then heads back toward the other end of the trace.

 

5) When it reaches the other end, the voltage has risen only maybe half of the way to its final value (in a normal I2C environment with ordinary GPIO transistors driving the line).

 

6) So, a scope with good sensitivity and bandwidth MIGHT see a small upwards "hitch" in the leading edge.

 

 

7) Once the rising voltage approaches the logic hi level the current through the pull up resistor decreases and the voltage rise slows enough that makes reflexions less likely. You see a ringing at the edge of a pulse when the output is a push-pull type. In case of I2C the corner is rounded by this current decrease. When the resistor is large, the rounding is so evident that it limits the I2C speed.

 

Another reason why it does not matter where you place the pull-up resistor is that the slave shorts the buss too. So even if you do magics by placing the resistor at the slave side, you only fix half of the problem. Should you place two resistors one at each end ? Then what about a buss with more than two devices connected in a star ? My way is to place the resistor wherever makes the PCB routing easier.

 

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jgmdesign wrote:

The resistors must also be at the last device on your bus.  Not at the microcontroller.

 

For I2C/SMBus it does not matter where the pull-ups are, as there are transmitters & receivers at both ends of the link. In some typologies it may be helpful to place pull-ups at both ends, but there is no advantage to placing them at one end-or the other if only a single set is used, all other factors being equal. IF a device has a particularly high pin capacitance, it may be helpful to place the pull-ups closer to that device, to increase the slew-rate of the rising edge.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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I respectfully disagree.  A bus is a bus.  Where I would change my position is in a situation where you have multiple masters on the bus then I would say put 10k resistors on both ends of the bus, thus bringing the pull up down to 4k7 on each line.

 

If the bus is only a few CM on a PCB then yeah, I can see where it might not matter, but on a longer line at the higher speeds I2C is now approaching having a 6 inch(15cm) bus on a PCB, placing the resistors say mid way the signals AFTER that point where the pull ups are placed will not be the same as they are between the host and the point of pull up placement. 

 

So everyone feels that for the following two connections the signals will look the same no matter where you probe, no matter the length of the lines?

 

 

If the answer is yes then fine,  I still stand by my opinion, and I still respectfully disagree.

 

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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The I2C edge rate is intentionally slow to negate transmission line effects, so my take is you can place the resistors anywhere. The pullup resistors are there for operational reasons, not transmission line termination. Also consider i2C was designed for the likes of TVs on single sided pcbs, so the bus would hardly be considered a conduit for high speed signals.
Neverthess, one can get a nice storage scope to look at the signals on a given circuit and see if there are signal integrity issues. Move the resistors and repeat.

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I get what your saying jdmdesign, as I design my buses the same way because why not, I think its a good design practice.

 

That being said, since this discussion has be going on i have been reading up on the I2C bus, and nothing ever mentions that the pull ups should be located at the end of the bus.

 

This is how every article depicts an I2C Bus.

 

 

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For reference: NXP document UM10204, "I2C Bus Specification and User Manual", Rev 6, 6 April 2014 

 

https://www.nxp.com/docs/en/user...

 

There is nothing about driver slew rate limiting. There is no minimum rise/fall spec for normal speed!

 

But, given the electrical characteristics of the line and typical drivers, the location of the pull-ups simply do not make much difference until, maybe, you talk highspeed. 

 

So ... if some of you want to put them at the far end, it will work fine. If you want to put them in the middle - fine. Close to the master - fine. 

 

For me, personally, I don't see taking the time and effort to arrange the board layout to get them at the far end. If the layout is simple with them close to the master, I'll put them there. If the far end is a particularly easy location, I will put them there. For me, the key word on this is "easy".

 

West Coast Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Apr 6, 2019 - 04:38 AM
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jgmdesign wrote:

So everyone feels that for the following two connections the signals will look the same no matter where you probe, no matter the length of the lines?

 

Of course it will be different at different points. Nobody is claiming it will be exactly the same at all points along the transmission line. We are saying it doesn't matter.  There is no advantage to place the pull-ups at one end or the other, you just move the problem from one end to the other. If anything you get the best result over the length of the bus by placing them in the middle, thus averaging out the transmission line losses from one end to the other.

 

Look at the diagram Kuch posted above. Tell me now, looking at the drivers, how is it better to place resistors at one end over the other?  It isn't... There is no additional termination or other circuitry in the master that differentiates it from a slave, electrically.

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

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App Note AVR315 shows below.  It doesn't say explicitly to put the pull-up resistors at the end of the bus, but it seems to imply it. 

 

In my own experience where my boards have grown organically, I have put them at the first I2C device, usually an EEPROM, and then connected later I2C devices willy nilly as the board grew with no design.  Remember, I am the epitome of amateur.  Things seem to work OK, but I keep to 100 kHz so the high frequency effects West Coast Jim describes are reduced. 

 

I must say I sort of like East Coast Jim's comment of putting a 10k pull-up resistor on each end of the bus lines.  Gives it a nice symmetry, with a combined parallel resistance of 5K.

 

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The diagram isn't implying anything. They could have just as easily placed the resistors before device 1, it's just an artistic rendering, not a schematic or layout drawing. As most of us read right to left, the resistors were likely placed on the left as it seems natural. Also note the odd placement of the arrows on SDA and SCL, implying additional devices before "Device 1" and more devices after the resistors and "Device n"

Writing code is like having sex.... make one little mistake, and you're supporting it for life.

Last Edited: Sun. Apr 7, 2019 - 08:30 PM
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MarkThomas wrote:
It doesn't say explicitly to put the pull-up resistors at the end of the bus, but it seems to imply it. 
I don't pretend to be an electronic engineer but while in TWI we talk about master/slave the fact is that electronically, the device that is controlling the bus at any time is no different whether it's the master, slave 1 or slave 57. So surely the resistor placement is arbitrary? While it might be at the "other end" of the bus from master that might benefit it when it is in control then it is presumably close to slave 57 and won't be the same for that. I guess the "perfect bus" would have the resistors equidistant from every device on the bus? Just trying to picture that in my mind but it's a bit like trying to visually picture a tesseract or something ! Would it actually be "star" with the resistors right at the centre perhaps ?

Last Edited: Tue. Apr 9, 2019 - 09:39 AM