Why the two ranges for OSCCAL?

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Just curious if anyone knows.

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I am guessing that they cannot tune far enough with one "range" so they change something, add a cap with a switch or change currents, mid range to get a wider span.

 

As a side note, this appears to be open loop, controlled only by the register value, and NOT a PLL. Guessing that it is a "plain" CMOS multivibrator.

 

Just a guess.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Mar 23, 2019 - 09:07 PM
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Your guess is probably right Jim!

 

I had made the mistake of altering OSCCAL by trying to make an ATMEGA325 a little more accurate at 5V since I think they calibrate it at 3V / 25 deg C and I wanted to use it at 5V.  I was using:

 

OSCCAL-=8;

Which works lovely with my test board, but in another board it speeds up the clock by 28%.  My theory is that it was on the edge of the two ranges and the subtraction of 8 pushed it into the higher part of the other range.

 

I just took it out, but I was wondering if this would work:

 

adjust=8;
while (OSCCAL!=0 && OSCCAL!=0x80 && adjust)
  {
    OSCCAL--;
    adjust--;
  }

Obviously this would only work in the subtraction direction.  I'd have to change the tests to !=0xff anf !=0x7f if adding.

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The idea of OSCCAL is you do a per board calibration in the factory then put the value for each into its EEPROM then at power on you read that and load it into OSCCAL. Don't expect one value to work for all.

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alank2 wrote:
Just curious if anyone knows.

This has been discussed at some length in the past.  Search it out.

 

Don't you need to tell us which model is of concern to you? 

The later-mentioned '325?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Sun. Mar 24, 2019 - 12:45 PM
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clawson wrote:

The idea of OSCCAL is you do a per board calibration in the factory then put the value for each into its EEPROM then at power on you read that and load it into OSCCAL. Don't expect one value to work for all.

 

I was hoping that it could also be used for a slight tweak to improve accuracy such as moving it from calibrated for 3V to calibrated for 5V.  I know it won't be perfect unless each board is done individually, but if an improvement could be made with no effort...

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theusch wrote:

Don't you need to tell us which model is of concern to you? 

The later-mentioned '325?

 

Your graph shows one range.  Here is the one I see in the 325 datasheet:

 

Are some single range and others dual range?

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If the split ones always split at 128 couldn't you simply test for OSCCAL being close and take avoiding action. That raises another question : is the "step" a fixed offset?

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That is exactly what I was thinking clawson - I had a code snippet in post #3 above that I was thinking about.  I don't think the offset is exactly fixed based on the graph, but workable perhaps.

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Going down it looks like the value below 128 is maybe 96 or something? Going up it looks like the value above 128 is 184 or something though it's not exactly linear! If you are adjusting by - 8 I guess you only need concern yourself (specifically) with values in the range 128 to 136? (subtract an additional 32)

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I agree; that is part of the problem in that you don't know what any given IC"s OSCCAL will be or what range it will be in.  Given what I was trying to do, just adjust the nominal 8MHz for 5V instead of 3V, it shouldn't be a big OSCCAL change so I was thinking alter it so long as it doesn't change ranges.  Perhaps I'll try it on a sample of chips and see what it works out.  Thanks!

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Jim's theory in #2 seems the most likely.
I would just accept the Factory calibration and move on. It should be good enough for 5V.
.
Some older chips have a split range. Most modern chips seem to have a single smooth range.
I am surprised by -8 difference in OSCCAL. You simply have to test for the discontinuity.
.
I would assume that you do a program and test. If it is that important, you can perform the calibration in your test.
If the factory gives 128-136, the factory should have jumped to the lower range.
.
In practice punters are going to use 8Mhz or 7.3728Mhz. It is unlikely that you attempt a higher baud-friendly value.
.
David.

Last Edited: Sun. Mar 24, 2019 - 04:04 PM
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alank2 wrote:
Are some single range and others dual range?

Ummm....

alank2 wrote:
that is part of the problem in that you don't know what any given IC"s OSCCAL will be or what range it will be in.

Ummm, again...if those variables were not variables, then OSCCAL or equivalent would not be needed.

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Not all devices have the dual range e.g. ATtiny4/5/9/10, ATmega8/16, etc.

 

The two ranges give a finer step where they overlap, near the nominal frequency, allowing better calibration in that neighbourhood, while still allowing calibration far outside the nominal.  Where the ranges overlap, for every OSCCAL value in the lower curve, there is a corresponding value in the upper curve which is a partial step (less than one LSB or either range) higher or lower than just moving to the next step within the same range.  Fully profiling the entire range of OSCCAL values during production (or within the app at runtime) can yield the best value under those conditions.

 

clawson wrote:
though it's not exactly linear
It's linear w.r.t. period.

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I've never understood this (attiny13a)

There are separate calibration bytes for 4.8 and 9.6 MHz

operation but only one is automatically loaded during reset (see section “Calibration Bytes” on

page 105). This is because the only difference between 4.8 MHz and 9.6 MHz mode is an internal

clock divider.

 

under cal bytes:

There is a separate calibration byte for the internal oscillator in 4.8 MHz mode of operation but

this data is not loaded automatically.

 

Ok, only one is loaded ...the other is not needed since there is a divide by 2 internal divider.  Ok, so when is the other one used (or why is it needed, if there is this divider)?  If it is cal'd for 9.6, then it is inherently cal'd  for 4.8 due to the divider.

Their conflicting explanation leaves a lot to be desired!

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

Last Edited: Sun. Mar 24, 2019 - 09:30 PM
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avrcandies wrote:

I've never understood this (attiny13a)

There are separate calibration bytes for 4.8 and 9.6 MHz

operation but only one is automatically loaded during reset....

Their conflicting explanation leaves a lot to be desired!

Before starting another design, I carefully reviewed the ATtiny13A datasheet and ended up taking more than five pages of notes about such design "warts": to remember and possibly work around. Sometimes, I don't think you actually design in a part, rather, you trick it into doing what you want it to do.

- John

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Here's my oneupmanship. What's the deal with this on the A4U xmegas:

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I believe that is the little man, inside, periodically re-tuning the string. At 224, he is eating dinner.

- John