What made me ask about the role of delay counter that i found two arrows enter this block of delay counter one is watchdog oscillator and second arrow is the CK does the delay counter do extra role like enabling the CK to get out from tri-state buffer and the enabling of this buffer could be the the Timeout signal (Timeout signal It is like the key for the clock to go out from peripheral)
To summarize my question why CK enters the delay counter ?
To summarize my question why CK enters the delay counter ?
While the watchdog description of the datasheet usually says something about "separate oscillator", look in the datasheet for the description of "start-up time". What clock is used for that?
What model is being discussed?
What is the importance to you of this issue? Are you creating your own core in programmable logic? Are you creating a cycle-accurate simulator?
It would help to know from which AVR you have posted this diagram from. Some AVR's have a choice of more then one clock source, so the delay counter must be able to be fed from all clock sources.
Notice the CKSEL bits are also feed to the delay counter as well so it knows from which source it needs to use to produce the needed time delay.
Hope that helps.
Jim
A fragment from a representative datasheet has the CK term controlling the end of internal reset...
LOL -- so the next question is how is 4.1ms clocked? [I'd guess that the watchdog or similar 128kHz internal oscillator]
The delay timer lets you set the watchdog timeout.
The largest known prime number: 282589933-1
Without adult supervision. 
The delay timer lets you set the watchdog timeout.
I can't really agree with that. Anyway, OP's question seems to be about the CK term.
why CK enters the delay counter ?
the delay is for slow rising power, so reset don't get released to early.
Surely "CK" is "ClocK".
OP's question, as I read it, is what role CK (system clock) might have in reset logic shown. WD "delay" seems straightforward to me. I also puzzled a bit until I thought of SUT. I'd guess that OP realizes that CK is the system clock after the prescaler.
Thanks for respond but i am not asking if the delay counter is using separate Oscillator i already knew that ,but i am asking why CK enters block of delay counter
And for question of you sir why i am asking this question it is only to understand and to know what the thing that i am programming that help for me.
Notice the CKSEL bits are also feed to the delay counter as well so it knows from which source it needs to use to produce the needed time delay.
Hope that helps.
Jim
I am speaking about atmega32 , i knew that the aim that CKSEL it to feed to the delay counter for various clocks , but why it enters the clock itself to the block of delay counter.
I think your guess is not right because it is easy when the the delay counter is activated the clock will be activated and at the same time the counter will count until reach the dedicated value according to SUB and CKSEL fuses.
I knew all of this could be done with CKSEL and SUB fuses
,but i am asking why CK enters block of delay counter
As has been explained above this is all about SUT = Start Up Time. Crystals are resonant devices. A bit like when you rub a wet finger round the top of cut glass. After a while and after you have injected some energy (the friction of your finger on the glass) it starts to "sing". This is resonance. Quartz crystals are a bit like this. Another analogy is a child's swing or a swinging pendulum. You have to swing each back and firth a few times until they get into a constant "rhythm", this too is resonance.
So when you have quartz providing a clock to an AVR it is pulsed a few times and the pulses grow bigger and bigger until the quartz starts to resonate and produce really big pulses. This takes time (possibly 1,000s of cycles) so the "R" input into the "internal reset" flip flop is held in the "reset" state for some time after power is first applied. An internal clock (CK) ticks the delay counter to measure some long delay (maybe 65ms?) while R is held in reset then finally the delay counter times out and R is released and the reset signal is gated through.
I think your guess is not right
Which "guess" are you talking about?
but why it enters the clock itself to the block of delay counter.
I gave my "evidence", since the CK signal is used in reset-control logic. Remember that you are discussing a block diagram, and not an exhaustive schematic.
As I mentioned, I'd have a lot more interest if I know the purpose of this hunt.
An internal clock (CK) ticks the delay counter to measure some long delay (maybe 65ms?)
Well, I cannot agree. CK from that diagram is the system clock, not some independent internal clock like the watchdog. As I speculated, though, I'd thing the "4.1ms" is an independent clock.
TBH, I also don't have any idea why the delay timer receives a clock signal from both the watchdog oscillator and the system clock.
I mean, the signal from the watchdog makes perfect sense to give time for "warm-up" as mentioned in previous posts.
But the purpose of CK, I have no idea. Maybe it needs to be synchronized to the system clock for some reason?
I am speaking about atmega32 , i knew that the aim that CKSEL it to feed to the delay counter for various clocks , but why it enters the clock itself to the block of delay counter.
If you were designing a reset-release timer, would you check the CK was working , before you released the timer ?
Also, when you do release reset, that should be done SYNC with the system clock - otherwise all sorts of nasty effects can occur if some parts release on one edge, and other parts do not release until the next clock edge.
And for question of you sir why i am asking this question it is only to understand and to know what the thing that i am programming that help for me.
There is no need to follow every single line inside any MCU ( & especially the ones you have no control over), just relax and know that Atmel's designers are experienced at doing this, and know what they are doing...
There is no need to follow every single line inside any MCU ( & especially the ones you have no control over), just relax and know that Atmel's designers are experienced at doing this, and know what they are doing...
^^^That.
Plus, just because a line exists on a block diagram, it doesn't mean it actually exists in the chip.
Plus, just because a line exists on a block diagram, it doesn't mean it actually exists in the chip.
From where you get this Opinion , I am just wondering not criticizing!!!
A fragment from a representative datasheet has the CK term controlling the end of internal reset...
LOL -- so the next question is how is 4.1ms clocked? [I'd guess that the watchdog or similar 128kHz internal oscillator]
That is, in fact, a highly interesting, and highly esoteric, question. Just where does it get its 'milliseconds' from?
And, for every application I can think of, totally irrelevant, but interesting.
S.
Edited to add: I wonder if there should be a tolerance specification on that number. S.
The clock enters the counter to, err, clock it. How else would the counter ever change state if it were not clocked??
So what is the difference between CK and watchdog oscillator؟
I think this could be the solution for the case :
https://en.wikipedia.org/wiki/Oscillator_start-up_timer
This also explains why CK is entered to the block
But the purpose of CK, I have no idea. Maybe it needs to be synchronized to the system clock for some reason?
Because the SUT is expessed in units of CK (system clock) as well as some "hard" time.
I'm getting a bit frustrated. "Old geezer" bleeding through probably. What am I missing? OP asked about the CK term entering that delay block dealing with reset control. From the construction of the CK it seems apparent to me that this is the system clock. SUT is expressed [at least partially] in units of CK. SUT is a delay, so that block makes sense.
I'm certainly not a chip designer, but if it takes 6 clocks to wake from sleep then doesn't it make sense that it would be the system clock?
OP still hasn't said why this hunt is important. But now the last couple posts are educating us that start-up is involved. I'll just retire, as this stuff is apparently too complicated for my dementia.
