Interrupts Not Required

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No interrupts - all I/O is polled.

This book avoided interrupts; but it used an 8051, so maybe it had to.

"Patterns for time-triggered embedded systems" by Michael J Pont, from 2001, published by Pearson Education.
 

Mike

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mha11 wrote:

This book avoided interrupts; but it used an 8051, so maybe it had to.

 

The 8051 series actually has a more sophisticated interrupt system than the AVR as it has a two-level priority scheme. So no, it did not have to.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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Brian Fairchild wrote:
a more sophisticated interrupt system than the AVR as it has a two-level priority scheme
This is a bit like Monty Python's Four Yorkshiremen but doesn't the Xmega have a 3 level priority system? ;-)

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Add :

And the 8051 had bank switch of the registers (mostly used for interrups), think if r24-r31 on a AVR could be changed to r8-r15 just by flipping a bit ;)   

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Wish I could switch my bank that easily.

Four legs good, two legs bad, three legs stable.

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smiley

4 (including NMI for XMEGA PMIC)

3 with NMI for unified memory AVR (tinyAVR 0-series, tinyAVR 1-series, megaAVR 0-series)

 

"Dare to be naïve." - Buckminster Fuller

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unified memory AVR

?

The registers are moved from the memory map , so it should only be "changed memory AVR" devil 

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