slave select pin made me feel mystery and contradictory in SPI

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I marked two lines in Serial Peripheral Interface – SPI in avr datasheet , made me feel mystery and contradictory about SPI (salve select) pin

How that After each data packet,the Master will synchronize the Slave by pulling high the Slave Select, SS, line.  and at the same time the SPI interface has no automatic control of the SS line

 

 

I am living to bring up new earth ,and not to eat and destroy earth.

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Mohamed asaad wrote:
After each data packet,the Master will synchronize the Slave by pulling high the Slave Select, SS, line

You are the master, you decide if and when the SS line is controlled, the SPI has no control of any SS line.

Check the datasheet of the SPI slave device to decide how the SS line must be handled, and code as necessary. 

Hope that helps.

 

Jim

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i knew that from datasheet i have read all of SPI text, but my question how I have the control on the SS/ PIN and the master automatically  After each data packet, will synchronize the Slave by pulling high the Slave Select, SS, line, as the datasheet said.

I am living to bring up new earth ,and not to eat and destroy earth.

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The first quote is confusing.
Most SPI Slave devices react to /CS becoming active i.e. LOW.
It is this signal that enables Slave hardware and synchronises the Slave timing.
.
From a high level point of view, a Slave device often responds to different commands received from the Master.
Sometimes the Slave reacts to each individual SCK pulse.
Or it receives the full 8 bits before taking appropriate action e.g. change a register.
Or some commands are just absorbed by the Slave e.g. filling a Page buffer in an EEPROM.
Certain commands only get activated when /CS goes HIGH e.g. the Page Write in an EEPROM,
.
SPI is only a sinple low level protocol. Different Slaves might behave differently e.g. CS as active-high or different SPI mode#.
.
David.
.
Edit. With an AVR the Master can only control /CS in software. You have to ensure the timing is correct e.g. wait for last byte to complete before releasing /CS..
Many ARM chips can control /CS in hardware. e.g. you tell the ARM to send 1234 bytes of SPI with DMA. It releases /CS when it has completed the last byte.

Last Edited: Tue. Jan 1, 2019 - 02:30 PM
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There is no contradiction, "the Master"  in the first line refers to the full implementation on the master side including the code that will manually control SS.

/Lars

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what i understood that after shifting 8 bit packet  the ss pin is held to be high by circuit of spi .

did you mean that the first mentioned line means that me as a programmer who will set the line not the circuit 

I am living to bring up new earth ,and not to eat and destroy earth.

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Yes, that is what I mean.

/Lars

 

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Thank you for soldering my thinking 

I am living to bring up new earth ,and not to eat and destroy earth.

Last Edited: Tue. Jan 1, 2019 - 04:14 PM
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Please be aware:

 

WHEN the /SS line is changed depends on the slave. It is NOT necessary to set /SS high after every 8 bit packet! For example, many require a 2-byte transfer in which the master sends an address or function command as the first byte and data for the second byte. Or, that second byte is data returned by the slave. In such cases, the slave will REQUIRE that /SS stay low during the entire transfer. 

 

Thus that first quote line is NOT accurate. In fact, the transfer may require that /SS stay low for many bytes. This might be required to send a whole string of characters to a buffer in the slave (or read a string of characters back from the slave).

 

What IS important is the requirement that /SS be taken high at the end of the TRANSFER. If  that transfer is 1 byte, then raise /SS at the end of that byte. If it is 10 bytes. then you raise it after the 10th byte is complete.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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Thus that first quote line is NOT accurate

Intention is probably that a "data packet" is any number of bytes and not 8 bits (I get that from the 2nd quoted paragraph).

/Lars

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One would hope that is  what they mean, though the text is not clear about whether that refers to one byte or a sequence of bytes bounded by the assertion and de-assertion of the chip select.

 

Also, it is notable that they always refer to the chip select as /SS. On AVRs, there is a specific pin with that name (well, close, "SS"). But, what that REALLY refers to is the line that provides the chip selection for the  peripheral device being talked to. That is, the reference to "/SS" refers to any pin that is used for an SPI chip select function and not just the unique pin that is named "SS".

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Wed. Jan 2, 2019 - 02:18 AM
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Mohamed asaad wrote:
what i understood that after shifting 8 bit packet the ss pin is held to be high by circuit of spi .

 

Not Exactly,

The Master controls the /SS line.  AS already noted the master brings the /SS line high after the last byte leaves the SPI out line.  It is up to the master to know when this is.  By polling the SPI TXC flag if available is a good way to do this monitoring.

 

Now one good thing you might want to do is put a 10k pull up resistor on your /SS line so when your SPI Master processor is in Reset, or power up, the /SS line is held high so that your SPI slave does not false load ambiguous noise that may be on the data lines at power up/reset.  In this case then YES, the circuit would be holding the /SS line high.

 

East Coast Jim

 

 

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That why i feel that something is wrong about the 1st line thank you for strengthen my thoughts 

I am living to bring up new earth ,and not to eat and destroy earth.

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yah, now it becomes clear.

I am living to bring up new earth ,and not to eat and destroy earth.

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That is nice declaration 

I am living to bring up new earth ,and not to eat and destroy earth.