I hope this is a relevant place for this!
I am working with the ATTINY45 and i am having problems with the compiler not generating assembly part of the C code, which i observed when i had a look at the .lss file. The relevant C code snippet is as follows:
volatile uint16_t counter = 0;
volatile uint8_t flag_reg = 0;
#define msflag 0
#define setmsflag() flag_reg |= (1<<msflag)
#define clearmsflag() flag_reg &= ~(1<<msflag)
#define sflag 1
#define setsflag() flag_reg |= (1<<sflag)
#define clearsflag() flag_reg &= ~(1<<sflag)
ISR(TIMER0_COMPA_vect)
{
counter++;
// part where ms flag is checked
if ((flag_reg & (1<<msflag)) == 1)
{
if ((counter%50) == 0) PORTB = PORTB ^ (1<<3);
}
// part where s flag is checked
if ((flag_reg & (1<<sflag)) == 1)
{
if ((counter%500) == 0)
{
PORTB = PORTB ^ (1<<3);
counter = 1;
}
}
}
ISR(PCINT0_vect)
{
// if PB0 is grounded, respond to a Mode interrupt
if((PINB & (1<<0)) == 0)
{
// Mode interrupt
clearsflag();
setmsflag();
}
// if PB1 is grounded, respond to a Change interrupt
else if((PINB & (1<<1)) == 0)
{
//Change interrupt
clearmsflag();
setsflag();
}
}counter - a variable that increments every 2ms.
flag_reg - A register with abstract flag definitions.
msflag - a flag defined for the flag_reg variable(to refer to millisecond interrupts).
sflag - a flag defined for the flag_reg variable(to refer to second interrupts).
I have gone step by step to check that all my ISRs work and all my hardware(circuits) works as well. All pieces work properly individually.
My problem: Following part in my TIMER0_COMPA_vect ISR does not generate any assembly code:
if ((flag_reg & (1<<sflag)) == 1)
{
if ((counter%500) == 0)
{
PORTB = PORTB ^ (1<<3);
counter = 1;
}
}
This is the generated assembly code for reference:
1. Vector Loaction for TIMER0_COMPA_vect ISR in the vector table
14: 15 c0 rjmp .+42 ; 0x40 <__vector_10>
2. Assembly code for the TIMER0_COMPA_vect ISR
00000040 <__vector_10>:
PORTB &= ~(1<<3);
}
void LEDon()
{
PORTB |= (1<<3);
40: 1f 92 push r1
42: 0f 92 push r0
44: 0f b6 in r0, 0x3f ; 63
46: 0f 92 push r0
48: 11 24 eor r1, r1
4a: 5f 93 push r21
4c: 6f 93 push r22
4e: 7f 93 push r23
50: 8f 93 push r24
52: 9f 93 push r25
54: af 93 push r26
56: bf 93 push r27
58: 80 91 61 00 lds r24, 0x0061 ; 0x800061 <counter>
5c: 90 91 62 00 lds r25, 0x0062 ; 0x800062 <counter+0x1>
60: 01 96 adiw r24, 0x01 ; 1
62: 90 93 62 00 sts 0x0062, r25 ; 0x800062 <counter+0x1>
66: 80 93 61 00 sts 0x0061, r24 ; 0x800061 <counter>
6a: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <_edata>
6e: 80 ff sbrs r24, 0
70: 0d c0 rjmp .+26 ; 0x8c <__vector_10+0x4c>
72: 80 91 61 00 lds r24, 0x0061 ; 0x800061 <counter>
76: 90 91 62 00 lds r25, 0x0062 ; 0x800062 <counter+0x1>
7a: 62 e3 ldi r22, 0x32 ; 50
7c: 70 e0 ldi r23, 0x00 ; 0
7e: 59 d0 rcall .+178 ; 0x132 <__udivmodhi4>
80: 89 2b or r24, r25
82: 21 f4 brne .+8 ; 0x8c <__vector_10+0x4c>
84: 98 b3 in r25, 0x18 ; 24
86: 88 e0 ldi r24, 0x08 ; 8
88: 89 27 eor r24, r25
8a: 88 bb out 0x18, r24 ; 24
8c: 80 91 60 00 lds r24, 0x0060 ; 0x800060 <_edata>
90: bf 91 pop r27
92: af 91 pop r26
94: 9f 91 pop r25
96: 8f 91 pop r24
98: 7f 91 pop r23
9a: 6f 91 pop r22
9c: 5f 91 pop r21
9e: 0f 90 pop r0
a0: 0f be out 0x3f, r0 ; 63
a2: 0f 90 pop r0
a4: 1f 90 pop r1
a6: 18 95 reti
Thanks for the Help.
