Hi all I'm sorry in advance again for these basic question, I have searched the archives here and have learned much regarding my question as posted above but nothing that addresses some of the nuances of my misunderstanding or ignorance at this stage of learning.
Table 15-2. Relationship between the USICS[1:0] and USICLK Setting
USICS1 USICS0 USICLK Clock Source 4-bit Counter Clock Source
0 0 0 No Clock No Clock
0 0 1 Software clock strobe (USICLK) Software clock strobe (USICLK)
0 1 X Timer/Counter0 Compare Match Timer/Counter0 Compare Match
1 0 0 External, positive edge External, both edges
1 1 0 External, negative edge External, both edges
1 0 1 External, positive edge Software clock strobe (USITC)
1 1 1 External, negative edge Software clock strobe (USITC)
The above table taken from the Atmel datasheet for a ATTiny. What I would appreciate understanding with clarity is how I go about deciding when using an external clock what setting do I use? Do I use positive edge, negative edge, etc. I know I could push buttons and eventually make it work but that never satisfies me. What references do I need to refer to make these decisions?
Secondly referring to Atmel AVR312 (Using the USI Module as a slave) I have a 328 sending out a start condition, and I successfully enter
ISR(USI_START_vect) on the ATTiny I want to act as a slave.
I can step through the code and see that it recognizes the ID I have assigned, and then this following code I'm sure many of you are very familiar with;
//Set USI to send ACK
USIDR = 0;
USISR = USI_SLAVE_COUNT_ACK_USISR;
//Set USI to Start Condition Mode
USICR = USI_SLAVE_SET_START_COND_USICR;
USISR = USI_SLAVE_SET_START_COND_USISR;
The code is executed to set the register to count one clock cycle, pull the SDA line low, etc. Now it looks to me like the USI hardware is supposed to look after all this for me after I set the register. The USI hardware should be holding the SCL line low as well simplifying timing between master and slave.
Am I correct in my understanding thus far?
I never see this on the Logic Analyzer.
All I ever see on the analyzer is the Start Condition and then a NACK - Never the ACK I want to see...
I have the main routine continuously looping issuing a Start to said device. Would this Start be causing the USI to reset? I was and I guess still am making the assumption that this shouldn't matter as the USI has control of the SDA line for this time? Is this understanding flawed? I will of course try this morning not sending repeated starts from the master to test my understanding of this.
Edit: I'm currently reading AVR310 Using the USI Module as a I2C Slave. While this is not what I want to do the code here is amazingly helpful. I'm not sure why its not mentioned more when the AVR312 is cited? They are helpful to be looked at together? no?
I'm sorry I just bought my first scope and I'm learning how to set triggers - I'm finding this tricky for a newbie.
I'm also going to try "manually" setting the SDA line low for one cycle this morning to see what happens, I'm feeling like I'm hacking at it now though - with a club.
One last question and this is really quite a newbie question. It is my assumption that the idea of the i2C bus being set at a specific speed 100, 400, etc. that of course the speed difference between the components isn't a factor as a slave will essentially hold up the bus until it is completed its work. So in this it doesn't matter if my Master is a 328P running at 16Mhz and my ATTiny is running at 1Mhz.
Maybe this is far too much for one post. I'm just learning my away around this amazing resource of people and knowledge. I'm not even sure if I posted this in the right forum.