Datasheet Interpretation - E5 32kHz Oscillator

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Good evening all,

 

Just interested in how other interpret this section of the xmega E5 datasheet (Microchip RevA, p95)...

 

 

Do the table values C(Tosc1) & C(Tosc2) correspond to the circuit values C(L1) & C(L2)?

 

In the doc "AT01080: XMEGA E Schematic Checklist" the oscillator is claimed to have a typical C(load) of 3pF.  It is not clear whether this includes any parasitic pin capacitance.  A total C(load) of 3pF might imply C(L1) = C(L2) = 6pF.

Interestingly the 5.3 & 7.4 does sum to 3.08pF so this sounds plausible.

 

So do I include both values such that the total C(load) is 6pF or 3pF?

 

The motivation for this comes from a deployment of a 32.786kHz crystal with C(load) specified as 4pF.  Working on a oscillator load of 3pF, I figured some trace/pin parasitic C would add at least 1pF to make it about right.  If I add the 2 it can never be low enough to achieve 4pF.  My current board appears to be running slow which might indicate too much C. With no external C included I cannot subtract any.

 

I don't suspect the layout has much room for improvement;  the crystal is about 0603 size and mounted right square next to the xtal pins.  There is 2 footprints for load caps next to that (unpopulated) and the entire section is surrounded by GND plain along with solid plain underneath with a number of via stitches.

 

Any thoughts?

 

Steve

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This document may give you good results.

 

http://ww1.microchip.com/downloa...

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schtevo wrote:
My current board appears to be running slow which might indicate too much C.

Selecting and Testing 32 KHz Crystal Oscillators for Microchip AVR® Microcontrollers

AN2648

(page 14)

3.3 Measuring Effective Load Capacitance

...

Applying the capacitive load specified in the crystal data sheet will provide a frequency very close to the nominal frequency of 32768 Hz. If other capacitive loads are applied, the frequency will change. The frequency will increase if the capacitive load is decreased, and will decrease if the load is increased, as shown in Figure 3-9.

...

schtevo wrote:
Any thoughts?
MattairTech XMEGA E5 board has 6pF load capacitors for its specific 32KHz crystal.

http://www.mattairtech.com/images/MT-DB-X5/MT-DB-X5.png (top right)

Though XMEGA E5 isn't in AN2648 other XMEGA are; 12 recommended crystals.

 


AN2648 Selecting and Testing 32 KHz Crystal Oscillators for AVR Microcontrollers | Application Notes | Microchip Technology Inc.

ATxmega32E5 - 8-bit PIC Microcontrollers - Microcontrollers and Processors

MT-DB-X5 Atmel AVR XMEGA E 32-pin ATxmega32e5 development board

 

edit: typo

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Thu. Dec 6, 2018 - 12:41 PM
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schtevo wrote:
Interestingly the 5.3 & 7.4 does sum to 3.08pF so this sounds plausible.

Eh! They're not in series. You can't do:

 

                1

    ---------------------  = 3.09

         1            1

      ------  +  ------

       5.3         7.4

 

To me those parasitic Cs  look like a good match for a 6.5pF watch crystal. Perhaps you should swap out your 3pF or a 6.5pF.

 

 

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@ Kabasn & Chapman: I had looked at AN2648 and this is what lead me to believe the total load cap is a little high.

 

I can't find the specified xtal PN for that Mattair board but I'd bet it'd be 6pF.  With 2 external 6pF caps (in series?) = 3pF + the 3pF oscillator load or parasitic brings back to 6pF. But wait, seems I've got that method all wrong....

 

N.Winterbottom wrote:
Eh! They're not in series. You can't do:

                1

--------------------- = 3.09

   1          1

------ + ------

 5.3        7.4

Err.... Really?! Have I been living a lie all these years?  Adding (in reciprocal) the 2 standard load caps hanging of any xtal to GND has been the way to calculate as far as I've been aware.  Interestingly, the E5 datasheet lists a 6.5pF in the table for ESR requirements. A lower limit perhaps?

 

How do you arrive at 6.5pF?

 

Anyway, I've run the board on external power overnight (rather than just an hr or so) and will check the discrepancy shortly.  After that I'll send the clock out to an I/O pin and see if i can measure it more precisely.

 

Thanks,

Steve

Last Edited: Thu. Dec 6, 2018 - 06:26 PM
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The XmegaE5 app note has this

 

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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The caps ARE in series. The ground point just happens to be where the two caps connect to each other. 

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

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schtevo wrote:
Have I been living a lie all these years?

Many of the AppNotes I've read refer to a classical analysis of a parallel resonant circuit where the equations assume an L & C in parallel. The tendency then is to add the external caps as if they were in series.

 

This is clearly wrong. Just imagine if you replaced an external 12pF ceramic with a 10uF ceramic. As an engineer you just know it won't stand a chance of oscillating, but hey the equation says load capacitance is 12pF, what's wrong ?

 

The Maxim AppNote APPLICATION NOTE 2127 Modeling of Quartz Crystal seems to be on the right lines.