I try to get DPLL0/1 to run with XOSC1 (12 MHz). It seems Atmel Start does not calculate the Frequencies correctly.
Regarding to device DS, the DPLL Input freq must be < 3,4 MHz. When XOSC is selevted, it is divided by "2x(DIV+1)" (See DPLL Control B Register).
I Assume "Clock Divider" in Atmel Start should match that register bits. So set this to 5, would result in Divider of (2x(5+1) = 12). Using XOSC1 as input (12 MHz) should result in 12 MHz/12 = 1 MHz -> the DPLL input frequency should be 1 MHz.
However, in Atmel Start the Clock Divider Setting does not change anything in the output frequency calculation. In the picture below the output frequency should be (99+1) * 1 MHz = 100 MHz.
It is shown as 1200 Mhz (presumably calculated from (99+1) * 12 MHz) however. Thus the Generate Code function refuses to generate the Project (Internal Server Error).
I did other tests using 12 MHz to drive a Genclk and feed back a divided down clock to DPLL. In that case code is generated but the software will do an infinite loop waiting for the PLL Lock bit.
Has anybody successful used Atmel Start + E54 DPLL with XOSC as source?
All examples for E54 seem to use 12 MHz directly or DPLL with 32kHz clock input.