Solved: RTC code works on one PCB, but not the other

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Hey guys,

 

I'm pulling my hair out over here.  I'm trying to figure out why one PCB seems to run my RTC clock code without any problems, while the other one gets stuck trying to configure the timer2 registers.  I have two PCBs, which I will call V1  and V2.  V1 has some mistakes (not related to RTC circuitry) so I iterated out another PCB.  To my chagrin, the 2nd PCB I had made doesn't seem to work in terms of the RTC (though the other problems were resolved).

 

I'm using the ATmega 328PB on both boards.

 

Here is the schematic and screenshot of RTC subcircuit PCB layout for V1:

 

 

 

 

 

 

 

and here is the same for V2:

 

 

 

 

 

 

 

The main differences between the two PCBs are:

 

- V1 uses 0805 footprint caps C5 and C6 in the crystal oscillator subcircuit, while V2 uses 0402 footprint caps

- V1 does not have the ATmega328PB back plane grounded, while V2 does have the ATmega328PB back plane grounded

- V1 was a 4-layer board, with vias connecting the 5V input of the ATmega32PB to the 5V internal power plane while V2 is a 2-layer board with 5V trace routed directly to ATmega from buck converter (not pictured).

- V1 left some pins of the ATmega unconnected (floating) while V2 used all connections to the ATmega (the 4 unused pins in V1 were connected to plug detection pins of barrel jacks on V2)

 

 

I have a simple program that I constructed to test the RTC on V1.  It configures Timer2 to get clocked asynchronously from the external oscillator circuit using the recommended procedure as detailed on page 230 of the datasheet which says:

 

 

Here is my test program, which basically performs the above recipe, goes to sleep with timer2 overflow wakeup source, and then starts counting how many seconds have elapsed and toggling the on-board PCB LEDs with each timer2 overflow...

 

/*
* RTC_clock.cpp
*
* Created: 7/27/2018 11:47:09 AM
* Author : Boompy
*/

#include <avr/io.h>
#include <avr/sleep.h>
#include <avr/interrupt.h>

// #define STOP_PREMATURELY_AND_DUMP_TCNT2_CONTINUOUSLY

const byte ledPin1 = 5;   //PD5   //RED
const byte ledPin2 = 9;   //PB1   //GREEN
const byte ledPin3 = 10;  //PB2   //GREEN
const byte ledPin4 = 2;   //PD2   //GREEN

//The following macros are used to switch to asynchronous external RTC clock using
//the safe method described on page 230 of the ATmega328PB datasheet

//STEP 1 --> Disable the TC2 interrupts by clearing OCIE2x and TOIE2.
//Macro to disable timer 2 interrupts
#define DISABLE_TIMER2_INTERRUPTS    TIMSK2 &= ~( (1<<OCIE2A) | (1<<OCIE2B) | (1<<TOIE2) )

//STEP 2 --> Select clock source by setting AS2 as appropriate.
//Macro to configure timer 2 to clock from external RTC oscillator
#define SET_TIMER2_DISABLE_EXTERNAL_CLOCK_INPUT ASSR &= ~(1<<EXCLK)
#define SET_TIMER2_ASYNC_EXTERNAL_CRYSTAL ASSR |= (1<<AS2)

//STEP 3 --> Write new values to TCNT2, OCR2x, and TCCR2x.
/*
TCNT2 = TC2 Countrer Value register
OCR2A = TC2 Output Compare register A
OCR2B = TC2 Output Compare register B
TCCR2A = TC2 Control Register A
TCCR2B = TC2 Control Register B
*/
//Macro to set the clock prescaler to 128 (makes the timer/count tick at frequency of 256 Hz... overflow once per second!)
#define DISABLE_TIMER_COUNT_SYNCHRONIZATION_MODE  GTCCR &= ~(1<<TSM)
#define RESET_TIMER2_PRESCALER      GTCCR |= (1<<PSRASY)      //Page 245 - General Timer/Counter Control Register
#define TIMER2_PRESCALER_RESETTING  (GTCCR & (1<<PSRASY))     //Page 245
#define SET_TIMER2_PRESCALER_128    TCCR2B = 0b00000101       //Page 236 - Timer control register B

//STEP 4 --> To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
//Macro that returns true if the TCNT2 register is in the midst of being written to (means we can't acces it yet)
#define TIMER2_COUNTER_UPDATE_BUSY    ( ASSR & (1<<TCN2UB) )
//Macro that returns true if either of the OCR2x registers are in the midst of being written to
#define TIMER2_OUTPUT_COMPARE_UPDATE_BUSY  ( (ASSR & (1<<OCR2AUB)) | (ASSR & (1<<OCR2BUB)) )
//Macro that returns true if either of the TCCR2X (timer 2 control register X) is in the midst of being written to
#define TIMER2_CONTROL_UPDATE_BUSY    ( (ASSR & (1<<TCR2AUB)) | (ASSR & (1<<TCR2BUB)) )
//Macro that returns true if any of the temporary registers are currently in the process of being latched (i.e. not ready yet)
#define TIMER2_REGISTERS_LATCHING  (TIMER2_COUNTER_UPDATE_BUSY | TIMER2_OUTPUT_COMPARE_UPDATE_BUSY | TIMER2_COUNTER_UPDATE_BUSY)

//STEP 5 --> Clear the TC2 interrupt flags.
#define TIMER2_CLEAR_OUTPUT_COMPARE_A_INTERRUPT_FLAG  TIFR2 &= ~(1<<OCF2A)
#define TIMER2_CLEAR_OUTPUT_COMPARE_B_INTERRUPT_FLAG  TIFR2 &= ~(1<<OCF2B)
#define TIMER2_CLEAR_OVERFLOW_INTERRUPT_FLAG      TIFR2 &= ~(1<<TOV2)
// #define TIMER2_CLEAR_ALL_INTERRUPT_FLAGS        TIFR2 &= (0b11111000)
#define TIMER2_CLEAR_ALL_INTERRUPT_FLAGS        TIFR2 = (0b00000111)

//STEP 6 --> Enable interrupts, if needed.
#define TIMER2_ENABLE_TIMER_OVERFLOW_INTERRUPT    TIMSK2 |= (1<<TOIE2)

volatile uint32_t unixTime = 0;
volatile bool unhandled_timer_2_overflow = false;
volatile uint8_t led_state = LOW;

//ISR for timer 2 overflow
ISR(TIMER2_OVF_vect){
  unixTime++;
  unhandled_timer_2_overflow = true;
  led_state = !led_state;
}

void debugPrintTimer2Registers(){
  Serial.println("!!!!!!!!!!");
  Serial.println("Timer2 registers:");
  Serial.flush();
  Serial.print("TCCR2A =");
  Serial.println(TCCR2A, BIN);
  Serial.flush();
  Serial.print("TCCR2B =");
  Serial.println(TCCR2B, BIN);
  Serial.flush();
  Serial.print("TCNT2 =");
  Serial.println(TCNT2, BIN);
  Serial.flush();
  Serial.print("OCR2A =");
  Serial.println(OCR2A, BIN);
  Serial.flush();
  Serial.print("OCR2B =");
  Serial.println(OCR2B, BIN);
  Serial.flush();
  Serial.print("TIMSK2 =");
  Serial.println(TIMSK2, BIN);
  Serial.flush();
  Serial.print("TIFR2 =");
  Serial.println(TIFR2, BIN);
  Serial.flush();
  Serial.print("ASSR =");
  Serial.println(ASSR, BIN);
  Serial.flush();
  Serial.print("GTCCR =");
  Serial.println(GTCCR, BIN);
  Serial.flush();
  Serial.println("!!!!!!!!!!");

}

void setupRTC(){

  Serial.println();
  Serial.println();
  Serial.println("Setting up RTC...");
  Serial.println();

  debugPrintTimer2Registers();

  /*=============================================>>>>>
  = STEP 1 --> Disable the TC2 interrupts by clearing OCIE2x and TOIE2. =
  ===============================================>>>>>*/
  Serial.println("Step 1");
  Serial.println("Disable the TC2 interrupts by clearing OCIE2x and TOIE2");
  Serial.println("==========");
  Serial.flush();
  DISABLE_TIMER2_INTERRUPTS;

  debugPrintTimer2Registers();
  /*= End of STEP 1 --> Disable the TC2 interrupts by clearing OCIE2x and TOIE2. =*/
  /*=============================================<<<<<*/

  /*=============================================>>>>>
  = STEP 2 --> Select clock source by setting AS2 as appropriate. =
  ===============================================>>>>>*/
  Serial.println("==========");
  Serial.println("Step 2");
  Serial.println("Select clock source by setting AS2 as appropriate");
  Serial.println("==========");
  Serial.flush();
  SET_TIMER2_DISABLE_EXTERNAL_CLOCK_INPUT;
  SET_TIMER2_ASYNC_EXTERNAL_CRYSTAL;

  debugPrintTimer2Registers();
  /*= End of STEP 2 --> Select clock source by setting AS2 as appropriate. =*/
  /*=============================================<<<<<*/

  /*=============================================>>>>>
  = STEP 3 --> Write new values to TCNT2, OCR2x, and TCCR2x. =
  ===============================================>>>>>*/
  Serial.println("==========");
  Serial.println("Step 3");
  Serial.println("Write new values to TCNT2, OCR2x, and TCCR2x");
  Serial.println("==========");
  Serial.flush();

  TCCR2A = 0; //Clear any bits that are in TCCR2A
  TCCR2B = 0; //Clear any bits that are set in TCCR2B
  SET_TIMER2_PRESCALER_128;

  debugPrintTimer2Registers();
  /*= End of STEP 3 --> Write new values to TCNT2, OCR2x, and TCCR2x. =*/
  /*=============================================<<<<<*/

  #ifdef STOP_PREMATURELY_AND_DUMP_TCNT2_CONTINUOUSLY
  Serial.println("Dumping TCNT2 continuously:");
  while(1){
    Serial.println(TCNT2, DEC);
  };
  #endif

  /*=============================================>>>>>
  = STEP 4 --> To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. =
  ===============================================>>>>>*/
  Serial.println("==========");
  Serial.println("Step 4");
  Serial.println("Wait for TCN2xUB, OCR2xUB, and TCR2xUB");
  Serial.println("==========");
  Serial.flush();

  byte loopCount = 0;
  Serial.println("Waiting for TIMER2_REGISTERS_LATCHING... ");

  bool keepWaiting = true;
  byte waitLoops = 0;
  while(keepWaiting){

    if(waitLoops > 10){
      Serial.println("Giving up!  Something is wrong!");
      Serial.print("Here is TCNT2 -->");
      while(1){
        Serial.println(TCNT2, DEC);
        delay(10);
      }
    }

    keepWaiting = false;
    Serial.println("-----");
    if(TIMER2_COUNTER_UPDATE_BUSY){
      Serial.println("TIMER2_COUNTER_UPDATE_BUSY");
      keepWaiting = true;
    }
    if(TIMER2_OUTPUT_COMPARE_UPDATE_BUSY){
      Serial.println("TIMER2_OUTPUT_COMPARE_UPDATE_BUSY");
      keepWaiting = true;
    }
    if(TIMER2_CONTROL_UPDATE_BUSY){
      Serial.println("TIMER2_CONTROL_UPDATE_BUSY");
      keepWaiting = true;
    }

    Serial.print("ASSR = ");
    Serial.println(ASSR, BIN);
    Serial.flush();

    waitLoops++;

  };

  // while(TIMER2_REGISTERS_LATCHING){
  //   Serial.print("ASSR = ");
  //   Serial.println(ASSR, BIN);
  //   Serial.flush();
  //   loopCount++;
  //   if(loopCount == 10){
  //     Serial.println("ERROR --> TIMER2_REGISTERS_LATCHING");
  //     while(1);
  //   }
  // };

  debugPrintTimer2Registers();
  /*= End of STEP 4 --> To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB. =*/
  /*=============================================<<<<<*/

  /*=============================================>>>>>
  = STEP 5 --> Clear the TC2 interrupt flags. =
  ===============================================>>>>>*/
  Serial.println("==========");
  Serial.println("Step 5");
  Serial.println("Clear the TC2 interrupt flags");
  Serial.println("==========");
  Serial.flush();
  TIMER2_CLEAR_ALL_INTERRUPT_FLAGS;
  debugPrintTimer2Registers();
  /*= End of STEP 5 --> Clear the TC2 interrupt flags. =*/
  /*=============================================<<<<<*/

  /*=============================================>>>>>
  = Setup the prescaler =
  ===============================================>>>>>*/
  Serial.println("==========");
  Serial.println("Step 5 - custom");
  Serial.println("Reset timer2 prescaler");
  Serial.println("==========");
  Serial.flush();

  DISABLE_TIMER_COUNT_SYNCHRONIZATION_MODE; //Make sure that Timer/Counter Synchronization mode is disabled (allows prescaler reset bit to be cleared by hardware)
  RESET_TIMER2_PRESCALER; //Reset the prescaler

  Serial.println("Waiting for TIMER2_PRESCALER_RESETTING...");
  Serial.flush();
  //Wait for prescaler to be reset
  loopCount = 0;
  while(TIMER2_PRESCALER_RESETTING){
    Serial.print("GTCCR = ");
    Serial.println(GTCCR, BIN);
    Serial.flush();
    loopCount++;
    if(loopCount == 10){
      Serial.println("ERROR --> TIMER2_PRESCALER_RESETTING");
      while(1);
    }
    // delay(250);
  };

  debugPrintTimer2Registers();
  /*= End of Setup the prescaler =*/
  /*=============================================<<<<<*/

  //STEP 6 --> Enable interrupts, if needed.
  Serial.println("==========");
  Serial.println("Step 6");
  Serial.println("Enable TC2 overflow interrupt");
  Serial.println("==========");
  Serial.flush();
  TIMER2_ENABLE_TIMER_OVERFLOW_INTERRUPT;

  debugPrintTimer2Registers();

  Serial.println("Done setting up RTC!");

}

void setup(){

  //Setup UART for serial debugging
  Serial.begin(9600);
  Serial.println("Beginning setup");
  Serial.flush();

  delay(1100);  //Wait 1.1 seconds for the TC2 to stabilize

  setupRTC();

  //Setup LED output pins
  pinMode(ledPin1, OUTPUT);
  pinMode(ledPin2, OUTPUT);
  pinMode(ledPin3, OUTPUT);
  pinMode(ledPin4, OUTPUT);

  set_sleep_mode(SLEEP_MODE_PWR_SAVE);
  sei();  //Enable global interrupts

  Serial.println("Finished setup");
  Serial.println("==========");;
  Serial.flush();

}

void loop(){

  // Serial.println("Sleeping");
  // Serial.flush();
  //
  // sleep_mode();
  //AWAKE--------------

  //Change LEDs
  digitalWrite(ledPin1, led_state); //Turn the LED on or off, depending on setting
  digitalWrite(ledPin2, led_state); //Turn the LED on or off, depending on setting
  digitalWrite(ledPin3, led_state); //Turn the LED on or off, depending on setting
  digitalWrite(ledPin4, led_state); //Turn the LED on or off, depending on setting
  //Check if we woke up because of an RTC tick
  if(unhandled_timer_2_overflow){

    Serial.println("unhandled_timer_2_overflow !");
    Serial.flush();

    debugPrintTimer2Registers();

    unhandled_timer_2_overflow = false;
    //May as well do some useful stuff while we are waiting for the latch
    Serial.print("Unix time = ");
    Serial.println(unixTime, DEC);
    Serial.flush();

    Serial.print("ASSR = ");
    Serial.println(ASSR, BIN);
    Serial.flush();

    //To avoid re-entering sleep mode during this TOSC cycle, write something inconsequential to OCR2
    //and keep checking whether this value has been latched to OCR2 yet.  Once it has been latched,
    //it is safe to re-enter sleep mode
    OCR2A = 123;
    //Wait for TOSC cycle to complete (OCR2A gets latched)
    byte loopCount = 0;
    while(TIMER2_REGISTERS_LATCHING){
      loopCount++;
      Serial.print("Waiting for register latch... ASSR = ");
      Serial.println(ASSR, BIN);
      delay(250);
      Serial.flush();
      if(loopCount > 10){
        Serial.println("GIVING UP!  SOMETHING IS BROKEN!");
        while(1);
      }
    };
  }
}

 

Here is the debug output for PCB V1 with the STOP_PREMATURELY_AND_DUMP_TCNT2_CONTINUOUSLY flag not defined:

 

[Tue Sep 11 16:04:51.071 2018] 0025352048 [app.ATmega] TRACE:
[Tue Sep 11 16:04:51.071 2018] Beginning setup
[Tue Sep 11 16:04:52.181 2018] 0025353159 [app.ATmega] TRACE:
[Tue Sep 11 16:04:52.183 2018]
[Tue Sep 11 16:04:52.185 2018]
[Tue Sep 11 16:04:52.185 2018] Setting up RTC...
[Tue Sep 11 16:04:52.207 2018]
[Tue Sep 11 16:04:52.207 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.219 2018] Timer2 registers:
[Tue Sep 11 16:04:52.239 2018] TCCR2A =1
[Tue Sep 11 16:04:52.252 2018] TCCR2B =100
[Tue Sep 11 16:04:52.264 2018] TCNT2 =11010100
[Tue Sep 11 16:04:52.282 2018] OCR2A =0
[Tue Sep 11 16:04:52.292 2018] OCR2B =0
[Tue Sep 11 16:04:52.302 2018] TIMSK2 =0
[Tue Sep 11 16:04:52.314 2018] TIFR2 =111
[Tue Sep 11 16:04:52.326 2018] ASSR =0
[Tue Sep 11 16:04:52.336 2018] GTCCR =0
[Tue Sep 11 16:04:52.346 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.359 2018] Step 1
[Tue Sep 11 16:04:52.367 2018] Disable the TC2 interrupts by clearing OCIE2x and TOIE2
[Tue Sep 11 16:04:52.425 2018] ==========
[Tue Sep 11 16:04:52.437 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.452 2018] Timer2 registers:
[Tue Sep 11 16:04:52.470 2018] TCCR2A =1
[Tue Sep 11 16:04:52.482 2018] TCCR2B =100
[Tue Sep 11 16:04:52.497 2018] TCNT2 =10101000
[Tue Sep 11 16:04:52.512 2018] OCR2A =0
[Tue Sep 11 16:04:52.522 2018] OCR2B =0
[Tue Sep 11 16:04:52.534 2018] TIMSK2 =0
[Tue Sep 11 16:04:52.545 2018] TIFR2 =111
[Tue Sep 11 16:04:52.557 2018] ASSR =0
[Tue Sep 11 16:04:52.567 2018] GTCCR =0
[Tue Sep 11 16:04:52.577 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.589 2018] ==========
[Tue Sep 11 16:04:52.601 2018] Step 2
[Tue Sep 11 16:04:52.609 2018] Select clock source by setting AS2 as appropriate
[Tue Sep 11 16:04:52.662 2018] ==========
[Tue Sep 11 16:04:52.676 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.688 2018] Timer2 registers:
[Tue Sep 11 16:04:52.709 2018] TCCR2A =1
[Tue Sep 11 16:04:52.718 2018] TCCR2B =100
[Tue Sep 11 16:04:52.732 2018] TCNT2 =10010101
[Tue Sep 11 16:04:52.752 2018] OCR2A =0
[Tue Sep 11 16:04:52.761 2018] OCR2B =0
[Tue Sep 11 16:04:52.771 2018] TIMSK2 =0
[Tue Sep 11 16:04:52.781 2018] TIFR2 =111
[Tue Sep 11 16:04:52.795 2018] ASSR =100011
[Tue Sep 11 16:04:52.809 2018] GTCCR =0
[Tue Sep 11 16:04:52.819 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.832 2018] ==========
[Tue Sep 11 16:04:52.844 2018] Step 3
[Tue Sep 11 16:04:52.852 2018] Write new values to TCNT2, OCR2x, and TCCR2x
[Tue Sep 11 16:04:52.900 2018] ==========
[Tue Sep 11 16:04:52.912 2018] !!!!!!!!!!
[Tue Sep 11 16:04:52.925 2018] Timer2 registers:
[Tue Sep 11 16:04:52.945 2018] TCCR2A =0
[Tue Sep 11 16:04:52.955 2018] TCCR2B =101
[Tue Sep 11 16:04:52.969 2018] TCNT2 =10010101
[Tue Sep 11 16:04:52.987 2018] OCR2A =0
[Tue Sep 11 16:04:52.997 2018] OCR2B =0
[Tue Sep 11 16:04:53.007 2018] TIMSK2 =0
[Tue Sep 11 16:04:53.019 2018] TIFR2 =111
[Tue Sep 11 16:04:53.032 2018] ASSR =100011
[Tue Sep 11 16:04:53.046 2018] GTCCR =0
[Tue Sep 11 16:04:53.056 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.068 2018] ==========
[Tue Sep 11 16:04:53.080 2018] Step 4
[Tue Sep 11 16:04:53.089 2018] Wait for TCN2xUB, OCR2xUB, and TCR2xUB
[Tue Sep 11 16:04:53.131 2018] ==========
[Tue Sep 11 16:04:53.144 2018] Waiting for TIMER2_REGISTERS_LATCHING...
[Tue Sep 11 16:04:53.189 2018] -----
[Tue Sep 11 16:04:53.194 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:04:53.223 2018] ASSR = 100011
[Tue Sep 11 16:04:53.240 2018] -----
[Tue Sep 11 16:04:53.246 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:04:53.276 2018] ASSR = 100011
[Tue Sep 11 16:04:53.290 2018] -----
[Tue Sep 11 16:04:53.299 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:04:53.327 2018] ASSR = 100011
[Tue Sep 11 16:04:53.343 2018] -----
[Tue Sep 11 16:04:53.349 2018] ASSR = 100000
[Tue Sep 11 16:04:53.365 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.377 2018] Timer2 registers:
[Tue Sep 11 16:04:53.397 2018] TCCR2A =0
[Tue Sep 11 16:04:53.409 2018] TCCR2B =101
[Tue Sep 11 16:04:53.423 2018] TCNT2 =10011100
[Tue Sep 11 16:04:53.440 2018] OCR2A =0
[Tue Sep 11 16:04:53.451 2018] OCR2B =0
[Tue Sep 11 16:04:53.460 2018] TIMSK2 =0
[Tue Sep 11 16:04:53.472 2018] TIFR2 =111
[Tue Sep 11 16:04:53.484 2018] ASSR =100000
[Tue Sep 11 16:04:53.499 2018] GTCCR =0
[Tue Sep 11 16:04:53.508 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.521 2018] ==========
[Tue Sep 11 16:04:53.535 2018] Step 5
[Tue Sep 11 16:04:53.543 2018] Clear the TC2 interrupt flags
[Tue Sep 11 16:04:53.575 2018] ==========
[Tue Sep 11 16:04:53.586 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.599 2018] Timer2 registers:
[Tue Sep 11 16:04:53.620 2018] TCCR2A =0
[Tue Sep 11 16:04:53.630 2018] TCCR2B =101
[Tue Sep 11 16:04:53.644 2018] TCNT2 =11001000
[Tue Sep 11 16:04:53.662 2018] OCR2A =0
[Tue Sep 11 16:04:53.672 2018] OCR2B =0
[Tue Sep 11 16:04:53.682 2018] TIMSK2 =0
[Tue Sep 11 16:04:53.692 2018] TIFR2 =0
[Tue Sep 11 16:04:53.704 2018] ASSR =100000
[Tue Sep 11 16:04:53.719 2018] GTCCR =0
[Tue Sep 11 16:04:53.729 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.741 2018] ==========
[Tue Sep 11 16:04:53.753 2018] Step 5 - custom
[Tue Sep 11 16:04:53.771 2018] Reset timer2 prescaler
[Tue Sep 11 16:04:53.796 2018] ==========
[Tue Sep 11 16:04:53.808 2018] Waiting for TIMER2_PRESCALER_RESETTING...
[Tue Sep 11 16:04:53.852 2018] !!!!!!!!!!
[Tue Sep 11 16:04:53.864 2018] Timer2 registers:
[Tue Sep 11 16:04:53.885 2018] TCCR2A =0
[Tue Sep 11 16:04:53.896 2018] TCCR2B =101
[Tue Sep 11 16:04:53.909 2018] TCNT2 =1011
[Tue Sep 11 16:04:53.923 2018] OCR2A =0
[Tue Sep 11 16:04:53.933 2018] OCR2B =0
[Tue Sep 11 16:04:53.943 2018] TIMSK2 =0
[Tue Sep 11 16:04:53.956 2018] TIFR2 =111
[Tue Sep 11 16:04:53.969 2018] ASSR =100000
[Tue Sep 11 16:04:53.981 2018] GTCCR =0
[Tue Sep 11 16:04:53.992 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.006 2018] ==========
[Tue Sep 11 16:04:54.018 2018] Step 5
[Tue Sep 11 16:04:54.026 2018] Clear the TC2 interrupt flags
[Tue Sep 11 16:04:54.058 2018] ==========
[Tue Sep 11 16:04:54.070 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.082 2018] Timer2 registers:
[Tue Sep 11 16:04:54.103 2018] TCCR2A =0
[Tue Sep 11 16:04:54.113 2018] TCCR2B =101
[Tue Sep 11 16:04:54.127 2018] TCNT2 =1000011
[Tue Sep 11 16:04:54.143 2018] OCR2A =0
[Tue Sep 11 16:04:54.153 2018] OCR2B =0
[Tue Sep 11 16:04:54.163 2018] TIMSK2 =1
[Tue Sep 11 16:04:54.175 2018] TIFR2 =110
[Tue Sep 11 16:04:54.188 2018] ASSR =100000
[Tue Sep 11 16:04:54.202 2018] GTCCR =0
[Tue Sep 11 16:04:54.213 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.226 2018] Done setting up RTC!
[Tue Sep 11 16:04:54.248 2018] Finished setup
[Tue Sep 11 16:04:54.264 2018] ==========
[Tue Sep 11 16:04:54.276 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:54.309 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.321 2018] Timer2 registers:
[Tue Sep 11 16:04:54.340 2018] TCCR2A =0
[Tue Sep 11 16:04:54.351 2018] TCCR2B =101
[Tue Sep 11 16:04:54.365 2018] TCNT2 =10000000
[Tue Sep 11 16:04:54.381 2018] OCR2A =0
[Tue Sep 11 16:04:54.393 2018] OCR2B =0
[Tue Sep 11 16:04:54.404 2018] TIMSK2 =1
[Tue Sep 11 16:04:54.414 2018] TIFR2 =110
[Tue Sep 11 16:04:54.427 2018] ASSR =100000
[Tue Sep 11 16:04:54.442 2018] GTCCR =0
[Tue Sep 11 16:04:54.452 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.464 2018] Unix time = 1
[Tue Sep 11 16:04:54.480 2018] ASSR = 100000
[Tue Sep 11 16:04:54.495 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:54.862 2018] 0025355840 [app.ATmega] TRACE:
[Tue Sep 11 16:04:54.862 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:54.894 2018] !!!!!!!!!!
[Tue Sep 11 16:04:54.907 2018] Timer2 registers:
[Tue Sep 11 16:04:54.927 2018] TCCR2A =0
[Tue Sep 11 16:04:54.938 2018] TCCR2B =101
[Tue Sep 11 16:04:54.951 2018] TCNT2 =10110
[Tue Sep 11 16:04:54.966 2018] OCR2A =1111011
[Tue Sep 11 16:04:54.981 2018] OCR2B =0
[Tue Sep 11 16:04:54.991 2018] TIMSK2 =1
[Tue Sep 11 16:04:55.004 2018] TIFR2 =110
[Tue Sep 11 16:04:55.017 2018] ASSR =100000
[Tue Sep 11 16:04:55.030 2018] GTCCR =0
[Tue Sep 11 16:04:55.040 2018] !!!!!!!!!!
[Tue Sep 11 16:04:55.054 2018] Unix time = 2
[Tue Sep 11 16:04:55.068 2018] ASSR = 100000
[Tue Sep 11 16:04:55.084 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:55.863 2018] 0025356840 [app.ATmega] TRACE:
[Tue Sep 11 16:04:55.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:55.895 2018] !!!!!!!!!!
[Tue Sep 11 16:04:55.907 2018] Timer2 registers:
[Tue Sep 11 16:04:55.927 2018] TCCR2A =0
[Tue Sep 11 16:04:55.938 2018] TCCR2B =101
[Tue Sep 11 16:04:55.951 2018] TCNT2 =10110
[Tue Sep 11 16:04:55.966 2018] OCR2A =1111011
[Tue Sep 11 16:04:55.981 2018] OCR2B =0
[Tue Sep 11 16:04:55.992 2018] TIMSK2 =1
[Tue Sep 11 16:04:56.004 2018] TIFR2 =110
[Tue Sep 11 16:04:56.016 2018] ASSR =100000
[Tue Sep 11 16:04:56.030 2018] GTCCR =0
[Tue Sep 11 16:04:56.040 2018] !!!!!!!!!!
[Tue Sep 11 16:04:56.054 2018] Unix time = 3
[Tue Sep 11 16:04:56.068 2018] ASSR = 100000
[Tue Sep 11 16:04:56.084 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:56.862 2018] 0025357840 [app.ATmega] TRACE:
[Tue Sep 11 16:04:56.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:56.894 2018] !!!!!!!!!!
[Tue Sep 11 16:04:56.907 2018] Timer2 registers:
[Tue Sep 11 16:04:56.927 2018] TCCR2A =0
[Tue Sep 11 16:04:56.938 2018] TCCR2B =101
[Tue Sep 11 16:04:56.951 2018] TCNT2 =10110
[Tue Sep 11 16:04:56.965 2018] OCR2A =1111011
[Tue Sep 11 16:04:56.984 2018] OCR2B =0
[Tue Sep 11 16:04:56.992 2018] TIMSK2 =1
[Tue Sep 11 16:04:57.004 2018] TIFR2 =110
[Tue Sep 11 16:04:57.016 2018] ASSR =100000
[Tue Sep 11 16:04:57.030 2018] GTCCR =0
[Tue Sep 11 16:04:57.040 2018] !!!!!!!!!!
[Tue Sep 11 16:04:57.054 2018] Unix time = 4
[Tue Sep 11 16:04:57.068 2018] ASSR = 100000
[Tue Sep 11 16:04:57.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:57.862 2018] 0025358840 [app.ATmega] TRACE:
[Tue Sep 11 16:04:57.862 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:57.894 2018] !!!!!!!!!!
[Tue Sep 11 16:04:57.907 2018] Timer2 registers:
[Tue Sep 11 16:04:57.927 2018] TCCR2A =0
[Tue Sep 11 16:04:57.938 2018] TCCR2B =101
[Tue Sep 11 16:04:57.951 2018] TCNT2 =10110
[Tue Sep 11 16:04:57.965 2018] OCR2A =1111011
[Tue Sep 11 16:04:57.982 2018] OCR2B =0
[Tue Sep 11 16:04:57.992 2018] TIMSK2 =1
[Tue Sep 11 16:04:58.004 2018] TIFR2 =110
[Tue Sep 11 16:04:58.018 2018] ASSR =100000
[Tue Sep 11 16:04:58.030 2018] GTCCR =0
[Tue Sep 11 16:04:58.042 2018] !!!!!!!!!!
[Tue Sep 11 16:04:58.054 2018] Unix time = 5
[Tue Sep 11 16:04:58.069 2018] ASSR = 100000
[Tue Sep 11 16:04:58.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:58.863 2018] 0025359841 [app.ATmega] TRACE:
[Tue Sep 11 16:04:58.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:58.895 2018] !!!!!!!!!!
[Tue Sep 11 16:04:58.907 2018] Timer2 registers:
[Tue Sep 11 16:04:58.927 2018] TCCR2A =0
[Tue Sep 11 16:04:58.939 2018] TCCR2B =101
[Tue Sep 11 16:04:58.951 2018] TCNT2 =10110
[Tue Sep 11 16:04:58.966 2018] OCR2A =1111011
[Tue Sep 11 16:04:58.982 2018] OCR2B =0
[Tue Sep 11 16:04:58.993 2018] TIMSK2 =1
[Tue Sep 11 16:04:59.004 2018] TIFR2 =110
[Tue Sep 11 16:04:59.016 2018] ASSR =100000
[Tue Sep 11 16:04:59.031 2018] GTCCR =0
[Tue Sep 11 16:04:59.042 2018] !!!!!!!!!!
[Tue Sep 11 16:04:59.054 2018] Unix time = 6
[Tue Sep 11 16:04:59.070 2018] ASSR = 100000
[Tue Sep 11 16:04:59.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:04:59.862 2018] 0025360841 [app.ATmega] TRACE:
[Tue Sep 11 16:04:59.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:04:59.895 2018] !!!!!!!!!!
[Tue Sep 11 16:04:59.907 2018] Timer2 registers:
[Tue Sep 11 16:04:59.927 2018] TCCR2A =0
[Tue Sep 11 16:04:59.937 2018] TCCR2B =101
[Tue Sep 11 16:04:59.953 2018] TCNT2 =10110
[Tue Sep 11 16:04:59.966 2018] OCR2A =1111011
[Tue Sep 11 16:04:59.982 2018] OCR2B =0
[Tue Sep 11 16:04:59.993 2018] TIMSK2 =1
[Tue Sep 11 16:05:00.005 2018] TIFR2 =110
[Tue Sep 11 16:05:00.017 2018] ASSR =100000
[Tue Sep 11 16:05:00.030 2018] GTCCR =0
[Tue Sep 11 16:05:00.042 2018] !!!!!!!!!!
[Tue Sep 11 16:05:00.055 2018] Unix time = 7
[Tue Sep 11 16:05:00.069 2018] ASSR = 100000
[Tue Sep 11 16:05:00.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:05:00.862 2018] 0025361841 [app.ATmega] TRACE:
[Tue Sep 11 16:05:00.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:05:00.894 2018] !!!!!!!!!!
[Tue Sep 11 16:05:00.907 2018] Timer2 registers:
[Tue Sep 11 16:05:00.927 2018] TCCR2A =0
[Tue Sep 11 16:05:00.938 2018] TCCR2B =101
[Tue Sep 11 16:05:00.952 2018] TCNT2 =10110
[Tue Sep 11 16:05:00.967 2018] OCR2A =1111011
[Tue Sep 11 16:05:00.982 2018] OCR2B =0
[Tue Sep 11 16:05:00.992 2018] TIMSK2 =1
[Tue Sep 11 16:05:01.004 2018] TIFR2 =110
[Tue Sep 11 16:05:01.017 2018] ASSR =100000
[Tue Sep 11 16:05:01.031 2018] GTCCR =0
[Tue Sep 11 16:05:01.043 2018] !!!!!!!!!!
[Tue Sep 11 16:05:01.055 2018] Unix time = 8
[Tue Sep 11 16:05:01.069 2018] ASSR = 100000
[Tue Sep 11 16:05:01.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:05:01.863 2018] 0025362841 [app.ATmega] TRACE:
[Tue Sep 11 16:05:01.863 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:05:01.895 2018] !!!!!!!!!!
[Tue Sep 11 16:05:01.907 2018] Timer2 registers:
[Tue Sep 11 16:05:01.927 2018] TCCR2A =0
[Tue Sep 11 16:05:01.938 2018] TCCR2B =101
[Tue Sep 11 16:05:01.953 2018] TCNT2 =10110
[Tue Sep 11 16:05:01.966 2018] OCR2A =1111011
[Tue Sep 11 16:05:01.982 2018] OCR2B =0
[Tue Sep 11 16:05:01.992 2018] TIMSK2 =1
[Tue Sep 11 16:05:02.004 2018] TIFR2 =110
[Tue Sep 11 16:05:02.017 2018] ASSR =100000
[Tue Sep 11 16:05:02.030 2018] GTCCR =0
[Tue Sep 11 16:05:02.043 2018] !!!!!!!!!!
[Tue Sep 11 16:05:02.055 2018] Unix time = 9
[Tue Sep 11 16:05:02.069 2018] ASSR = 100000
[Tue Sep 11 16:05:02.085 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:05:02.864 2018] 0025363841 [app.ATmega] TRACE:
[Tue Sep 11 16:05:02.864 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:05:02.895 2018] !!!!!!!!!!
[Tue Sep 11 16:05:02.907 2018] Timer2 registers:
[Tue Sep 11 16:05:02.928 2018] TCCR2A =0
[Tue Sep 11 16:05:02.939 2018] TCCR2B =101
[Tue Sep 11 16:05:02.952 2018] TCNT2 =10110
[Tue Sep 11 16:05:02.966 2018] OCR2A =1111011
[Tue Sep 11 16:05:02.982 2018] OCR2B =0
[Tue Sep 11 16:05:02.992 2018] TIMSK2 =1
[Tue Sep 11 16:05:03.004 2018] TIFR2 =110
[Tue Sep 11 16:05:03.016 2018] ASSR =100000
[Tue Sep 11 16:05:03.032 2018] GTCCR =0
[Tue Sep 11 16:05:03.043 2018] !!!!!!!!!!
[Tue Sep 11 16:05:03.054 2018] Unix time = 10
[Tue Sep 11 16:05:03.071 2018] ASSR = 100000
[Tue Sep 11 16:05:03.087 2018] Waiting for register latch... ASSR = 100000
[Tue Sep 11 16:05:03.864 2018] 0025364841 [app.ATmega] TRACE:
[Tue Sep 11 16:05:03.864 2018] unhandled_timer_2_overflow !
[Tue Sep 11 16:05:03.895 2018] !!!!!!!!!!
[Tue Sep 11 16:05:03.907 2018] Timer2 registers:
[Tue Sep 11 16:05:03.928 2018] TCCR2A =0
[Tue Sep 11 16:05:03.938 2018] TCCR2B =101
[Tue Sep 11 16:05:03.952 2018] TCNT2 =10110
[Tue Sep 11 16:05:03.967 2018] OCR2A =1111011
[Tue Sep 11 16:05:03.982 2018] OCR2B =0
[Tue Sep 11 16:05:03.992 2018] TIMSK2 =1
[Tue Sep 11 16:05:04.004 2018] TIFR2 =110
[Tue Sep 11 16:05:04.017 2018] ASSR =100000
[Tue Sep 11 16:05:04.031 2018] GTCCR =0
[Tue Sep 11 16:05:04.043 2018] !!!!!!!!!!
[Tue Sep 11 16:05:04.054 2018] Unix time = 11
[Tue Sep 11 16:05:04.071 2018] ASSR = 100000
[Tue Sep 11 16:05:04.087 2018] Waiting for register latch... ASSR = 100000

 

and here is the output for PCB V2:

 

[Tue Sep 11 16:08:12.008 2018] 0025552983 [app.ATmega] TRACE:
[Tue Sep 11 16:08:12.008 2018] Beginning setup
[Tue Sep 11 16:08:13.105 2018] 0025554086 [app.ATmega] TRACE:
[Tue Sep 11 16:08:13.108 2018]
[Tue Sep 11 16:08:13.109 2018]
[Tue Sep 11 16:08:13.109 2018] Setting up RTC...
[Tue Sep 11 16:08:13.131 2018]
[Tue Sep 11 16:08:13.131 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.143 2018] Timer2 registers:
[Tue Sep 11 16:08:13.163 2018] TCCR2A =1
[Tue Sep 11 16:08:13.173 2018] TCCR2B =100
[Tue Sep 11 16:08:13.189 2018] TCNT2 =11010100
[Tue Sep 11 16:08:13.206 2018] OCR2A =0
[Tue Sep 11 16:08:13.216 2018] OCR2B =0
[Tue Sep 11 16:08:13.226 2018] TIMSK2 =0
[Tue Sep 11 16:08:13.238 2018] TIFR2 =111
[Tue Sep 11 16:08:13.250 2018] ASSR =0
[Tue Sep 11 16:08:13.258 2018] GTCCR =0
[Tue Sep 11 16:08:13.268 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.280 2018] Step 1
[Tue Sep 11 16:08:13.288 2018] Disable the TC2 interrupts by clearing OCIE2x and TOIE2
[Tue Sep 11 16:08:13.348 2018] ==========
[Tue Sep 11 16:08:13.361 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.373 2018] Timer2 registers:
[Tue Sep 11 16:08:13.392 2018] TCCR2A =1
[Tue Sep 11 16:08:13.404 2018] TCCR2B =100
[Tue Sep 11 16:08:13.418 2018] TCNT2 =10101000
[Tue Sep 11 16:08:13.434 2018] OCR2A =0
[Tue Sep 11 16:08:13.444 2018] OCR2B =0
[Tue Sep 11 16:08:13.454 2018] TIMSK2 =0
[Tue Sep 11 16:08:13.466 2018] TIFR2 =111
[Tue Sep 11 16:08:13.477 2018] ASSR =0
[Tue Sep 11 16:08:13.488 2018] GTCCR =0
[Tue Sep 11 16:08:13.499 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.511 2018] ==========
[Tue Sep 11 16:08:13.523 2018] Step 2
[Tue Sep 11 16:08:13.531 2018] Select clock source by setting AS2 as appropriate
[Tue Sep 11 16:08:13.583 2018] ==========
[Tue Sep 11 16:08:13.596 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.608 2018] Timer2 registers:
[Tue Sep 11 16:08:13.628 2018] TCCR2A =1
[Tue Sep 11 16:08:13.639 2018] TCCR2B =100
[Tue Sep 11 16:08:13.652 2018] TCNT2 =10010101
[Tue Sep 11 16:08:13.670 2018] OCR2A =0
[Tue Sep 11 16:08:13.680 2018] OCR2B =0
[Tue Sep 11 16:08:13.691 2018] TIMSK2 =0
[Tue Sep 11 16:08:13.703 2018] TIFR2 =111
[Tue Sep 11 16:08:13.715 2018] ASSR =100011
[Tue Sep 11 16:08:13.729 2018] GTCCR =0
[Tue Sep 11 16:08:13.740 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.752 2018] ==========
[Tue Sep 11 16:08:13.763 2018] Step 3
[Tue Sep 11 16:08:13.771 2018] Write new values to TCNT2, OCR2x, and TCCR2x
[Tue Sep 11 16:08:13.818 2018] ==========
[Tue Sep 11 16:08:13.832 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.844 2018] Timer2 registers:
[Tue Sep 11 16:08:13.862 2018] TCCR2A =0
[Tue Sep 11 16:08:13.875 2018] TCCR2B =101
[Tue Sep 11 16:08:13.889 2018] TCNT2 =10010101
[Tue Sep 11 16:08:13.905 2018] OCR2A =0
[Tue Sep 11 16:08:13.915 2018] OCR2B =0
[Tue Sep 11 16:08:13.925 2018] TIMSK2 =0
[Tue Sep 11 16:08:13.936 2018] TIFR2 =111
[Tue Sep 11 16:08:13.949 2018] ASSR =100011
[Tue Sep 11 16:08:13.963 2018] GTCCR =0
[Tue Sep 11 16:08:13.974 2018] !!!!!!!!!!
[Tue Sep 11 16:08:13.986 2018] ==========
[Tue Sep 11 16:08:14.000 2018] Step 4
[Tue Sep 11 16:08:14.008 2018] Wait for TCN2xUB, OCR2xUB, and TCR2xUB
[Tue Sep 11 16:08:14.048 2018] ==========
[Tue Sep 11 16:08:14.061 2018] Waiting for TIMER2_REGISTERS_LATCHING...
[Tue Sep 11 16:08:14.104 2018] -----
[Tue Sep 11 16:08:14.111 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.141 2018] ASSR = 100011
[Tue Sep 11 16:08:14.155 2018] -----
[Tue Sep 11 16:08:14.163 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.193 2018] ASSR = 100011
[Tue Sep 11 16:08:14.208 2018] -----
[Tue Sep 11 16:08:14.214 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.244 2018] ASSR = 100011
[Tue Sep 11 16:08:14.258 2018] -----
[Tue Sep 11 16:08:14.267 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.294 2018] ASSR = 100011
[Tue Sep 11 16:08:14.311 2018] -----
[Tue Sep 11 16:08:14.317 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.345 2018] ASSR = 100011
[Tue Sep 11 16:08:14.362 2018] -----
[Tue Sep 11 16:08:14.370 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.398 2018] ASSR = 100011
[Tue Sep 11 16:08:14.412 2018] -----
[Tue Sep 11 16:08:14.420 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.449 2018] ASSR = 100011
[Tue Sep 11 16:08:14.465 2018] -----
[Tue Sep 11 16:08:14.471 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.500 2018] ASSR = 100011
[Tue Sep 11 16:08:14.515 2018] -----
[Tue Sep 11 16:08:14.523 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.551 2018] ASSR = 100011
[Tue Sep 11 16:08:14.568 2018] -----
[Tue Sep 11 16:08:14.575 2018] TIMER2_CONTROL_UPDATE_BUSY
[Tue Sep 11 16:08:14.602 2018] ASSR = 100011
[Tue Sep 11 16:08:14.618 2018] Giving up!  Something is wrong!

 

 

As you can see, it appears that the TCR2AUB and TCR2BUB bits of the ASSR register never get cleared (which would indicate that the TCCR2A and TCCR2B control registers are not being latched) on PCB V2.

 

If i enable the STOP_PREMATURELY_AND_DUMP_TCNT2_CONTINUOUSLY debug mode, here is the output for PCB V1:

 

 

[Tue Sep 11 16:21:18.135 2018] 0000488818 [app.ATmega] TRACE:
[Tue Sep 11 16:21:18.135 2018] Beginning setup
[Tue Sep 11 16:21:19.245 2018] 0000489929 [app.ATmega] TRACE:
[Tue Sep 11 16:21:19.248 2018]
[Tue Sep 11 16:21:19.251 2018]
[Tue Sep 11 16:21:19.251 2018] Setting up RTC...
[Tue Sep 11 16:21:19.271 2018]
[Tue Sep 11 16:21:19.271 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.284 2018] Timer2 registers:
[Tue Sep 11 16:21:19.303 2018] TCCR2A =1
[Tue Sep 11 16:21:19.315 2018] TCCR2B =100
[Tue Sep 11 16:21:19.328 2018] TCNT2 =11010100
[Tue Sep 11 16:21:19.347 2018] OCR2A =0
[Tue Sep 11 16:21:19.357 2018] OCR2B =0
[Tue Sep 11 16:21:19.367 2018] TIMSK2 =0
[Tue Sep 11 16:21:19.379 2018] TIFR2 =111
[Tue Sep 11 16:21:19.390 2018] ASSR =0
[Tue Sep 11 16:21:19.401 2018] GTCCR =0
[Tue Sep 11 16:21:19.411 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.422 2018] Step 1
[Tue Sep 11 16:21:19.430 2018] Disable the TC2 interrupts by clearing OCIE2x and TOIE2
[Tue Sep 11 16:21:19.490 2018] ==========
[Tue Sep 11 16:21:19.501 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.513 2018] Timer2 registers:
[Tue Sep 11 16:21:19.535 2018] TCCR2A =1
[Tue Sep 11 16:21:19.547 2018] TCCR2B =100
[Tue Sep 11 16:21:19.558 2018] TCNT2 =10100111
[Tue Sep 11 16:21:19.577 2018] OCR2A =0
[Tue Sep 11 16:21:19.586 2018] OCR2B =0
[Tue Sep 11 16:21:19.597 2018] TIMSK2 =0
[Tue Sep 11 16:21:19.609 2018] TIFR2 =111
[Tue Sep 11 16:21:19.621 2018] ASSR =0
[Tue Sep 11 16:21:19.631 2018] GTCCR =0
[Tue Sep 11 16:21:19.642 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.654 2018] ==========
[Tue Sep 11 16:21:19.665 2018] Step 2
[Tue Sep 11 16:21:19.673 2018] Select clock source by setting AS2 as appropriate
[Tue Sep 11 16:21:19.727 2018] ==========
[Tue Sep 11 16:21:19.741 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.752 2018] Timer2 registers:
[Tue Sep 11 16:21:19.771 2018] TCCR2A =1
[Tue Sep 11 16:21:19.783 2018] TCCR2B =100
[Tue Sep 11 16:21:19.797 2018] TCNT2 =10010101
[Tue Sep 11 16:21:19.813 2018] OCR2A =0
[Tue Sep 11 16:21:19.826 2018] OCR2B =0
[Tue Sep 11 16:21:19.835 2018] TIMSK2 =0
[Tue Sep 11 16:21:19.846 2018] TIFR2 =111
[Tue Sep 11 16:21:19.859 2018] ASSR =100011
[Tue Sep 11 16:21:19.873 2018] GTCCR =0
[Tue Sep 11 16:21:19.883 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.896 2018] ==========
[Tue Sep 11 16:21:19.908 2018] Step 3
[Tue Sep 11 16:21:19.916 2018] Write new values to TCNT2, OCR2x, and TCCR2x
[Tue Sep 11 16:21:19.964 2018] ==========
[Tue Sep 11 16:21:19.976 2018] !!!!!!!!!!
[Tue Sep 11 16:21:19.989 2018] Timer2 registers:
[Tue Sep 11 16:21:20.008 2018] TCCR2A =0
[Tue Sep 11 16:21:20.020 2018] TCCR2B =101
[Tue Sep 11 16:21:20.033 2018] TCNT2 =10010101
[Tue Sep 11 16:21:20.051 2018] OCR2A =0
[Tue Sep 11 16:21:20.062 2018] OCR2B =0
[Tue Sep 11 16:21:20.072 2018] TIMSK2 =0
[Tue Sep 11 16:21:20.082 2018] TIFR2 =111
[Tue Sep 11 16:21:20.096 2018] ASSR =100011
[Tue Sep 11 16:21:20.110 2018] GTCCR =0
[Tue Sep 11 16:21:20.121 2018] !!!!!!!!!!
[Tue Sep 11 16:21:20.133 2018] Dumping TCNT2 continuously:
[Tue Sep 11 16:21:20.163 2018] 149
[Tue Sep 11 16:21:20.167 2018] 149
[Tue Sep 11 16:21:20.172 2018] 149
[Tue Sep 11 16:21:20.178 2018] 149
[Tue Sep 11 16:21:20.182 2018] 149
[Tue Sep 11 16:21:20.189 2018] 149
[Tue Sep 11 16:21:20.193 2018] 149
[Tue Sep 11 16:21:20.199 2018] 149
[Tue Sep 11 16:21:20.203 2018] 149
[Tue Sep 11 16:21:20.210 2018] 149
[Tue Sep 11 16:21:20.213 2018] 149
[Tue Sep 11 16:21:20.219 2018] 149
[Tue Sep 11 16:21:20.225 2018] 149
[Tue Sep 11 16:21:20.230 2018] 149
[Tue Sep 11 16:21:20.236 2018] 149
[Tue Sep 11 16:21:20.240 2018] 149
[Tue Sep 11 16:21:20.246 2018] 149
[Tue Sep 11 16:21:20.251 2018] 149
[Tue Sep 11 16:21:20.255 2018] 149
[Tue Sep 11 16:21:20.260 2018] 149
[Tue Sep 11 16:21:20.265 2018] 149
[Tue Sep 11 16:21:20.271 2018] 149
[Tue Sep 11 16:21:20.276 2018] 149
[Tue Sep 11 16:21:20.282 2018] 149
[Tue Sep 11 16:21:20.286 2018] 149
[Tue Sep 11 16:21:20.292 2018] 149
[Tue Sep 11 16:21:20.298 2018] 149
[Tue Sep 11 16:21:20.302 2018] 149
[Tue Sep 11 16:21:20.306 2018] 149
[Tue Sep 11 16:21:20.313 2018] 149
[Tue Sep 11 16:21:20.318 2018] 149
[Tue Sep 11 16:21:20.323 2018] 149
[Tue Sep 11 16:21:20.328 2018] 149
[Tue Sep 11 16:21:20.333 2018] 149
[Tue Sep 11 16:21:20.339 2018] 149
[Tue Sep 11 16:21:20.343 2018] 149
[Tue Sep 11 16:21:20.348 2018] 149
[Tue Sep 11 16:21:20.352 2018] 149
[Tue Sep 11 16:21:20.358 2018] 149
[Tue Sep 11 16:21:20.364 2018] 149
[Tue Sep 11 16:21:20.369 2018] 149
[Tue Sep 11 16:21:20.375 2018] 149
[Tue Sep 11 16:21:20.379 2018] 149
[Tue Sep 11 16:21:20.385 2018] 149
[Tue Sep 11 16:21:20.388 2018] 149
[Tue Sep 11 16:21:20.394 2018] 149
[Tue Sep 11 16:21:20.399 2018] 150
[Tue Sep 11 16:21:20.406 2018] 150
[Tue Sep 11 16:21:20.412 2018] 150
[Tue Sep 11 16:21:20.416 2018] 150
[Tue Sep 11 16:21:20.423 2018] 150
[Tue Sep 11 16:21:20.426 2018] 151
[Tue Sep 11 16:21:20.431 2018] 151
[Tue Sep 11 16:21:20.435 2018] 151
[Tue Sep 11 16:21:20.441 2018] 151
[Tue Sep 11 16:21:20.446 2018] 152
[Tue Sep 11 16:21:20.452 2018] 152
[Tue Sep 11 16:21:20.458 2018] 152
[Tue Sep 11 16:21:20.462 2018] 153
[Tue Sep 11 16:21:20.467 2018] 153
[Tue Sep 11 16:21:20.471 2018] 153
[Tue Sep 11 16:21:20.477 2018] 154
[Tue Sep 11 16:21:20.482 2018] 154
[Tue Sep 11 16:21:20.487 2018] 155
[Tue Sep 11 16:21:20.492 2018] 155
[Tue Sep 11 16:21:20.498 2018] 156
[Tue Sep 11 16:21:20.505 2018] 156
[Tue Sep 11 16:21:20.509 2018] 157
[Tue Sep 11 16:21:20.515 2018] 157
[Tue Sep 11 16:21:20.518 2018] 158
[Tue Sep 11 16:21:20.524 2018] 158
[Tue Sep 11 16:21:20.529 2018] 159
[Tue Sep 11 16:21:20.534 2018] 159
[Tue Sep 11 16:21:20.539 2018] 160
[Tue Sep 11 16:21:20.545 2018] 160
[Tue Sep 11 16:21:20.551 2018] 161
[Tue Sep 11 16:21:20.555 2018] 161
[Tue Sep 11 16:21:20.560 2018] 162
[Tue Sep 11 16:21:20.565 2018] 163
[Tue Sep 11 16:21:20.570 2018] 164
[Tue Sep 11 16:21:20.575 2018] 164
[Tue Sep 11 16:21:20.580 2018] 166
[Tue Sep 11 16:21:20.585 2018] 167
[Tue Sep 11 16:21:20.591 2018] 168
[Tue Sep 11 16:21:20.598 2018] 170
[Tue Sep 11 16:21:20.601 2018] 171
[Tue Sep 11 16:21:20.607 2018] 172
[Tue Sep 11 16:21:20.611 2018] 174
[Tue Sep 11 16:21:20.617 2018] 175
[Tue Sep 11 16:21:20.622 2018] 176
[Tue Sep 11 16:21:20.628 2018] 178
[Tue Sep 11 16:21:20.632 2018] 179
[Tue Sep 11 16:21:20.638 2018] 180
[Tue Sep 11 16:21:20.643 2018] 182
[Tue Sep 11 16:21:20.647 2018] 183
[Tue Sep 11 16:21:20.653 2018] 184
[Tue Sep 11 16:21:20.658 2018] 186
[Tue Sep 11 16:21:20.663 2018] 187
[Tue Sep 11 16:21:20.668 2018] 188
[Tue Sep 11 16:21:20.674 2018] 190
[Tue Sep 11 16:21:20.678 2018] 191
[Tue Sep 11 16:21:20.683 2018] 192
[Tue Sep 11 16:21:20.689 2018] 193
[Tue Sep 11 16:21:20.695 2018] 195
[Tue Sep 11 16:21:20.700 2018] 196
[Tue Sep 11 16:21:20.705 2018] 197
[Tue Sep 11 16:21:20.711 2018] 199
[Tue Sep 11 16:21:20.715 2018] 200
[Tue Sep 11 16:21:20.721 2018] 201
[Tue Sep 11 16:21:20.724 2018] 203
[Tue Sep 11 16:21:20.730 2018] 204
[Tue Sep 11 16:21:20.737 2018] 205
[Tue Sep 11 16:21:20.741 2018] 207
[Tue Sep 11 16:21:20.747 2018] 208
[Tue Sep 11 16:21:20.752 2018] 209
[Tue Sep 11 16:21:20.757 2018] 211
[Tue Sep 11 16:21:20.761 2018] 212
[Tue Sep 11 16:21:20.766 2018] 213
[Tue Sep 11 16:21:20.770 2018] 215
[Tue Sep 11 16:21:20.777 2018] 216
[Tue Sep 11 16:21:20.782 2018] 217
[Tue Sep 11 16:21:20.787 2018] 219
[Tue Sep 11 16:21:20.794 2018] 220
[Tue Sep 11 16:21:20.798 2018] 221
[Tue Sep 11 16:21:20.804 2018] 223
[Tue Sep 11 16:21:20.807 2018] 224
[Tue Sep 11 16:21:20.813 2018] 225
[Tue Sep 11 16:21:20.818 2018] 227
[Tue Sep 11 16:21:20.824 2018] 228
[Tue Sep 11 16:21:20.829 2018] 229
[Tue Sep 11 16:21:20.834 2018] 231
[Tue Sep 11 16:21:20.840 2018] 232
[Tue Sep 11 16:21:20.844 2018] 233
[Tue Sep 11 16:21:20.849 2018] 234
[Tue Sep 11 16:21:20.853 2018] 236
[Tue Sep 11 16:21:20.860 2018] 237
[Tue Sep 11 16:21:20.864 2018] 238
[Tue Sep 11 16:21:20.870 2018] 240
[Tue Sep 11 16:21:20.876 2018] 241
[Tue Sep 11 16:21:20.880 2018] 242
[Tue Sep 11 16:21:20.885 2018] 244
[Tue Sep 11 16:21:20.890 2018] 245
[Tue Sep 11 16:21:20.896 2018] 246
[Tue Sep 11 16:21:20.901 2018] 248
[Tue Sep 11 16:21:20.906 2018] 249
[Tue Sep 11 16:21:20.911 2018] 250
[Tue Sep 11 16:21:20.917 2018] 252
[Tue Sep 11 16:21:20.923 2018] 253
[Tue Sep 11 16:21:20.927 2018] 254
[Tue Sep 11 16:21:20.932 2018] 0
[Tue Sep 11 16:21:20.934 2018] 0
[Tue Sep 11 16:21:20.940 2018] 1
[Tue Sep 11 16:21:20.941 2018] 2
[Tue Sep 11 16:21:20.945 2018] 3
[Tue Sep 11 16:21:20.947 2018] 4
[Tue Sep 11 16:21:20.951 2018] 4
[Tue Sep 11 16:21:20.953 2018] 5
[Tue Sep 11 16:21:20.957 2018] 6
[Tue Sep 11 16:21:20.961 2018] 7
[Tue Sep 11 16:21:20.963 2018] 8
[Tue Sep 11 16:21:20.967 2018] 8
[Tue Sep 11 16:21:20.968 2018] 9
[Tue Sep 11 16:21:20.972 2018] 10
[Tue Sep 11 16:21:20.976 2018] 11
[Tue Sep 11 16:21:20.980 2018] 12
[Tue Sep 11 16:21:20.985 2018] 13
[Tue Sep 11 16:21:20.989 2018] 14
[Tue Sep 11 16:21:20.993 2018] 15
[Tue Sep 11 16:21:20.998 2018] 16
[Tue Sep 11 16:21:21.002 2018] 17
[Tue Sep 11 16:21:21.006 2018] 18
[Tue Sep 11 16:21:21.010 2018] 19
[Tue Sep 11 16:21:21.013 2018] 21
[Tue Sep 11 16:21:21.017 2018] 22
[Tue Sep 11 16:21:21.021 2018] 23
[Tue Sep 11 16:21:21.026 2018] 24
[Tue Sep 11 16:21:21.030 2018] 25
[Tue Sep 11 16:21:21.034 2018] 26
[Tue Sep 11 16:21:21.038 2018] 27
[Tue Sep 11 16:21:21.042 2018] 28
[Tue Sep 11 16:21:21.046 2018] 29

 

 

As you can see, after the prescaler in TCCR2B gets latched, the timer begins incrementing again (it sits at 149 for about 230 ms and then starts incrementing again)

 

Here is the same output for PCB V2:

 

[Tue Sep 11 16:18:12.361 2018] 0000303041 [app.ATmega] TRACE:
[Tue Sep 11 16:18:12.361 2018] Beginning setup
[Tue Sep 11 16:18:13.467 2018] 0000304147 [app.ATmega] TRACE:
[Tue Sep 11 16:18:13.467 2018]
[Tue Sep 11 16:18:13.471 2018]
[Tue Sep 11 16:18:13.471 2018] Setting up RTC...
[Tue Sep 11 16:18:13.490 2018]
[Tue Sep 11 16:18:13.492 2018] !!!!!!!!!!
[Tue Sep 11 16:18:13.505 2018] Timer2 registers:
[Tue Sep 11 16:18:13.523 2018] TCCR2A =1
[Tue Sep 11 16:18:13.536 2018] TCCR2B =100
[Tue Sep 11 16:18:13.550 2018] TCNT2 =11010100
[Tue Sep 11 16:18:13.565 2018] OCR2A =0
[Tue Sep 11 16:18:13.575 2018] OCR2B =0
[Tue Sep 11 16:18:13.588 2018] TIMSK2 =0
[Tue Sep 11 16:18:13.598 2018] TIFR2 =111
[Tue Sep 11 16:18:13.609 2018] ASSR =0
[Tue Sep 11 16:18:13.620 2018] GTCCR =0
[Tue Sep 11 16:18:13.631 2018] !!!!!!!!!!
[Tue Sep 11 16:18:13.642 2018] Step 1
[Tue Sep 11 16:18:13.650 2018] Disable the TC2 interrupts by clearing OCIE2x and TOIE2
[Tue Sep 11 16:18:13.710 2018] ==========
[Tue Sep 11 16:18:13.722 2018] !!!!!!!!!!
[Tue Sep 11 16:18:13.733 2018] Timer2 registers:
[Tue Sep 11 16:18:13.754 2018] TCCR2A =1
[Tue Sep 11 16:18:13.766 2018] TCCR2B =100
[Tue Sep 11 16:18:13.777 2018] TCNT2 =10100111
[Tue Sep 11 16:18:13.796 2018] OCR2A =0
[Tue Sep 11 16:18:13.807 2018] OCR2B =0
[Tue Sep 11 16:18:13.816 2018] TIMSK2 =0
[Tue Sep 11 16:18:13.828 2018] TIFR2 =111
[Tue Sep 11 16:18:13.841 2018] ASSR =0
[Tue Sep 11 16:18:13.849 2018] GTCCR =0
[Tue Sep 11 16:18:13.860 2018] !!!!!!!!!!
[Tue Sep 11 16:18:13.872 2018] ==========
[Tue Sep 11 16:18:13.885 2018] Step 2
[Tue Sep 11 16:18:13.893 2018] Select clock source by setting AS2 as appropriate
[Tue Sep 11 16:18:13.945 2018] ==========
[Tue Sep 11 16:18:13.958 2018] !!!!!!!!!!
[Tue Sep 11 16:18:13.970 2018] Timer2 registers:
[Tue Sep 11 16:18:13.990 2018] TCCR2A =1
[Tue Sep 11 16:18:14.001 2018] TCCR2B =100
[Tue Sep 11 16:18:14.015 2018] TCNT2 =10010101
[Tue Sep 11 16:18:14.033 2018] OCR2A =0
[Tue Sep 11 16:18:14.043 2018] OCR2B =0
[Tue Sep 11 16:18:14.053 2018] TIMSK2 =0
[Tue Sep 11 16:18:14.064 2018] TIFR2 =111
[Tue Sep 11 16:18:14.074 2018] ASSR =100011
[Tue Sep 11 16:18:14.091 2018] GTCCR =0
[Tue Sep 11 16:18:14.101 2018] !!!!!!!!!!
[Tue Sep 11 16:18:14.113 2018] ==========
[Tue Sep 11 16:18:14.127 2018] Step 3
[Tue Sep 11 16:18:14.134 2018] Write new values to TCNT2, OCR2x, and TCCR2x
[Tue Sep 11 16:18:14.180 2018] ==========
[Tue Sep 11 16:18:14.194 2018] !!!!!!!!!!
[Tue Sep 11 16:18:14.206 2018] Timer2 registers:
[Tue Sep 11 16:18:14.225 2018] TCCR2A =0
[Tue Sep 11 16:18:14.236 2018] TCCR2B =101
[Tue Sep 11 16:18:14.251 2018] TCNT2 =10010101
[Tue Sep 11 16:18:14.267 2018] OCR2A =0
[Tue Sep 11 16:18:14.276 2018] OCR2B =0
[Tue Sep 11 16:18:14.287 2018] TIMSK2 =0
[Tue Sep 11 16:18:14.300 2018] TIFR2 =111
[Tue Sep 11 16:18:14.313 2018] ASSR =100011
[Tue Sep 11 16:18:14.326 2018] GTCCR =0
[Tue Sep 11 16:18:14.336 2018] !!!!!!!!!!
[Tue Sep 11 16:18:14.348 2018] Dumping TCNT2 continuously:
[Tue Sep 11 16:18:14.378 2018] 149
[Tue Sep 11 16:18:14.384 2018] 149
[Tue Sep 11 16:18:14.389 2018] 149
[Tue Sep 11 16:18:14.395 2018] 149
[Tue Sep 11 16:18:14.398 2018] 149
[Tue Sep 11 16:18:14.404 2018] 149
[Tue Sep 11 16:18:14.408 2018] 149
[Tue Sep 11 16:18:14.415 2018] 149
[Tue Sep 11 16:18:14.420 2018] 149
[Tue Sep 11 16:18:14.425 2018] 149
[Tue Sep 11 16:18:14.431 2018] 149
[Tue Sep 11 16:18:14.435 2018] 149
[Tue Sep 11 16:18:14.440 2018] 149
[Tue Sep 11 16:18:14.444 2018] 149
[Tue Sep 11 16:18:14.450 2018] 149
[Tue Sep 11 16:18:14.455 2018] 149
[Tue Sep 11 16:18:14.460 2018] 149
[Tue Sep 11 16:18:14.465 2018] 149
[Tue Sep 11 16:18:14.471 2018] 149
[Tue Sep 11 16:18:14.477 2018] 149
[Tue Sep 11 16:18:14.481 2018] 149
[Tue Sep 11 16:18:14.487 2018] 149
[Tue Sep 11 16:18:14.491 2018] 149
[Tue Sep 11 16:18:14.497 2018] 149
[Tue Sep 11 16:18:14.502 2018] 149
[Tue Sep 11 16:18:14.508 2018] 149
[Tue Sep 11 16:18:14.512 2018] 149
[Tue Sep 11 16:18:14.518 2018] 149
[Tue Sep 11 16:18:14.522 2018] 149
[Tue Sep 11 16:18:14.527 2018] 149
[Tue Sep 11 16:18:14.533 2018] 149
[Tue Sep 11 16:18:14.538 2018] 149
[Tue Sep 11 16:18:14.543 2018] 149
[Tue Sep 11 16:18:14.548 2018] 149
[Tue Sep 11 16:18:14.554 2018] 149
[Tue Sep 11 16:18:14.558 2018] 149
[Tue Sep 11 16:18:14.565 2018] 149
[Tue Sep 11 16:18:14.567 2018] 149
[Tue Sep 11 16:18:14.573 2018] 149
[Tue Sep 11 16:18:14.577 2018] 149
[Tue Sep 11 16:18:14.584 2018] 149
[Tue Sep 11 16:18:14.590 2018] 149
[Tue Sep 11 16:18:14.595 2018] 149
[Tue Sep 11 16:18:14.601 2018] 149
[Tue Sep 11 16:18:14.605 2018] 149
[Tue Sep 11 16:18:14.610 2018] 149
[Tue Sep 11 16:18:14.615 2018] 149
[Tue Sep 11 16:18:14.620 2018] 149
[Tue Sep 11 16:18:14.626 2018] 149
[Tue Sep 11 16:18:14.630 2018] 149
[Tue Sep 11 16:18:14.635 2018] 149
[Tue Sep 11 16:18:14.641 2018] 149
[Tue Sep 11 16:18:14.645 2018] 149
[Tue Sep 11 16:18:14.651 2018] 149
[Tue Sep 11 16:18:14.656 2018] 149
[Tue Sep 11 16:18:14.660 2018] 149
[Tue Sep 11 16:18:14.666 2018] 149
[Tue Sep 11 16:18:14.671 2018] 149
[Tue Sep 11 16:18:14.678 2018] 149
[Tue Sep 11 16:18:14.682 2018] 149
[Tue Sep 11 16:18:14.688 2018] 149
[Tue Sep 11 16:18:14.692 2018] 149
[Tue Sep 11 16:18:14.697 2018] 149
[Tue Sep 11 16:18:14.701 2018] 149
[Tue Sep 11 16:18:14.708 2018] 149
[Tue Sep 11 16:18:14.714 2018] 149
[Tue Sep 11 16:18:14.718 2018] 149
[Tue Sep 11 16:18:14.724 2018] 149
[Tue Sep 11 16:18:14.728 2018] 149
[Tue Sep 11 16:18:14.734 2018] 149
[Tue Sep 11 16:18:14.737 2018] 149
[Tue Sep 11 16:18:14.743 2018] 149
[Tue Sep 11 16:18:14.748 2018] 149
[Tue Sep 11 16:18:14.753 2018] 149
[Tue Sep 11 16:18:14.758 2018] 149
[Tue Sep 11 16:18:14.764 2018] 149
[Tue Sep 11 16:18:14.770 2018] 149
[Tue Sep 11 16:18:14.774 2018] 149
[Tue Sep 11 16:18:14.780 2018] 149
[Tue Sep 11 16:18:14.784 2018] 149
[Tue Sep 11 16:18:14.790 2018] 149
[Tue Sep 11 16:18:14.796 2018] 149
[Tue Sep 11 16:18:14.800 2018] 149
[Tue Sep 11 16:18:14.805 2018] 149
[Tue Sep 11 16:18:14.812 2018] 149
[Tue Sep 11 16:18:14.815 2018] 149
[Tue Sep 11 16:18:14.820 2018] 149
[Tue Sep 11 16:18:14.824 2018] 149
[Tue Sep 11 16:18:14.831 2018] 149
[Tue Sep 11 16:18:14.836 2018] 149
[Tue Sep 11 16:18:14.842 2018] 149
[Tue Sep 11 16:18:14.847 2018] 149
[Tue Sep 11 16:18:14.851 2018] 149
[Tue Sep 11 16:18:14.857 2018] 149
[Tue Sep 11 16:18:14.860 2018] 149
[Tue Sep 11 16:18:14.866 2018] 149
[Tue Sep 11 16:18:14.872 2018] 149
[Tue Sep 11 16:18:14.877 2018] 149
[Tue Sep 11 16:18:14.882 2018] 149
[Tue Sep 11 16:18:14.888 2018] 149
[Tue Sep 11 16:18:14.894 2018] 149
[Tue Sep 11 16:18:14.898 2018] 149
[Tue Sep 11 16:18:14.903 2018] 149
[Tue Sep 11 16:18:14.908 2018] 149
[Tue Sep 11 16:18:14.914 2018] 149
[Tue Sep 11 16:18:14.917 2018] 149
[Tue Sep 11 16:18:14.924 2018] 149
[Tue Sep 11 16:18:14.928 2018] 149
[Tue Sep 11 16:18:14.934 2018] 149
[Tue Sep 11 16:18:14.938 2018] 149
[Tue Sep 11 16:18:14.943 2018] 149
[Tue Sep 11 16:18:14.949 2018] 149
[Tue Sep 11 16:18:14.953 2018] 149
[Tue Sep 11 16:18:14.959 2018] 149
[Tue Sep 11 16:18:14.964 2018] 149
[Tue Sep 11 16:18:14.971 2018] 149
[Tue Sep 11 16:18:14.975 2018] 149
[Tue Sep 11 16:18:14.981 2018] 149
[Tue Sep 11 16:18:14.984 2018] 149
[Tue Sep 11 16:18:14.990 2018] 149
[Tue Sep 11 16:18:14.995 2018] 149
[Tue Sep 11 16:18:15.001 2018] 149
[Tue Sep 11 16:18:15.005 2018] 149
[Tue Sep 11 16:18:15.011 2018] 149
[Tue Sep 11 16:18:15.017 2018] 149
[Tue Sep 11 16:18:15.021 2018] 149
[Tue Sep 11 16:18:15.026 2018] 149
[Tue Sep 11 16:18:15.030 2018] 149
[Tue Sep 11 16:18:15.036 2018] 149
[Tue Sep 11 16:18:15.041 2018] 149
[Tue Sep 11 16:18:15.047 2018] 149
[Tue Sep 11 16:18:15.051 2018] 149
[Tue Sep 11 16:18:15.057 2018] 149
[Tue Sep 11 16:18:15.063 2018] 149
[Tue Sep 11 16:18:15.067 2018] 149
[Tue Sep 11 16:18:15.073 2018] 149
[Tue Sep 11 16:18:15.077 2018] 149
[Tue Sep 11 16:18:15.083 2018] 149
[Tue Sep 11 16:18:15.088 2018] 149
[Tue Sep 11 16:18:15.094 2018] 149
[Tue Sep 11 16:18:15.098 2018] 149
[Tue Sep 11 16:18:15.104 2018] 149
[Tue Sep 11 16:18:15.108 2018] 149
[Tue Sep 11 16:18:15.113 2018] 149
[Tue Sep 11 16:18:15.117 2018] 149
[Tue Sep 11 16:18:15.123 2018] 149
[Tue Sep 11 16:18:15.129 2018] 149
[Tue Sep 11 16:18:15.134 2018] 149
[Tue Sep 11 16:18:15.140 2018] 149
[Tue Sep 11 16:18:15.144 2018] 149
[Tue Sep 11 16:18:15.150 2018] 149
[Tue Sep 11 16:18:15.153 2018] 149
[Tue Sep 11 16:18:15.160 2018] 149
[Tue Sep 11 16:18:15.165 2018] 149
[Tue Sep 11 16:18:15.171 2018] 149
[Tue Sep 11 16:18:15.175 2018] 149
[Tue Sep 11 16:18:15.181 2018] 149
[Tue Sep 11 16:18:15.188 2018] 149
[Tue Sep 11 16:18:15.191 2018] 149
[Tue Sep 11 16:18:15.196 2018] 149
[Tue Sep 11 16:18:15.201 2018] 149
[Tue Sep 11 16:18:15.206 2018] 149
[Tue Sep 11 16:18:15.211 2018] 149
[Tue Sep 11 16:18:15.217 2018] 149
[Tue Sep 11 16:18:15.221 2018] 149
[Tue Sep 11 16:18:15.227 2018] 149
[Tue Sep 11 16:18:15.231 2018] 149
[Tue Sep 11 16:18:15.236 2018] 149
[Tue Sep 11 16:18:15.240 2018] 149
[Tue Sep 11 16:18:15.247 2018] 149
[Tue Sep 11 16:18:15.252 2018] 149
[Tue Sep 11 16:18:15.258 2018] 149
[Tue Sep 11 16:18:15.264 2018] 149
[Tue Sep 11 16:18:15.268 2018] 149
[Tue Sep 11 16:18:15.274 2018] 149
[Tue Sep 11 16:18:15.277 2018] 149
[Tue Sep 11 16:18:15.283 2018] 149
[Tue Sep 11 16:18:15.287 2018] 149
[Tue Sep 11 16:18:15.293 2018] 149
[Tue Sep 11 16:18:15.298 2018] 149
[Tue Sep 11 16:18:15.303 2018] 149
[Tue Sep 11 16:18:15.310 2018] 149
[Tue Sep 11 16:18:15.314 2018] 149
[Tue Sep 11 16:18:15.319 2018] 149
[Tue Sep 11 16:18:15.324 2018] 149
[Tue Sep 11 16:18:15.329 2018] 149
[Tue Sep 11 16:18:15.333 2018] 149
[Tue Sep 11 16:18:15.339 2018] 149
[Tue Sep 11 16:18:15.344 2018] 149
[Tue Sep 11 16:18:15.349 2018] 149
[Tue Sep 11 16:18:15.355 2018] 149
[Tue Sep 11 16:18:15.361 2018] 149
[Tue Sep 11 16:18:15.367 2018] 149
[Tue Sep 11 16:18:15.370 2018] 149
[Tue Sep 11 16:18:15.376 2018] 149
[Tue Sep 11 16:18:15.380 2018] 149
[Tue Sep 11 16:18:15.386 2018] 149
[Tue Sep 11 16:18:15.391 2018] 149
[Tue Sep 11 16:18:15.397 2018] 149
[Tue Sep 11 16:18:15.401 2018] 149
[Tue Sep 11 16:18:15.407 2018] 149
[Tue Sep 11 16:18:15.410 2018] 149
[Tue Sep 11 16:18:15.416 2018] 149
[Tue Sep 11 16:18:15.420 2018] 149
[Tue Sep 11 16:18:15.427 2018] 149
[Tue Sep 11 16:18:15.432 2018] 149
[Tue Sep 11 16:18:15.438 2018] 149
[Tue Sep 11 16:18:15.443 2018] 149
[Tue Sep 11 16:18:15.447 2018] 149
[Tue Sep 11 16:18:15.453 2018] 149
[Tue Sep 11 16:18:15.457 2018] 149
[Tue Sep 11 16:18:15.464 2018] 149
[Tue Sep 11 16:18:15.468 2018] 149
[Tue Sep 11 16:18:15.473 2018] 149
[Tue Sep 11 16:18:15.478 2018] 149
[Tue Sep 11 16:18:15.485 2018] 149
[Tue Sep 11 16:18:15.490 2018] 149
[Tue Sep 11 16:18:15.494 2018] 149
[Tue Sep 11 16:18:15.500 2018] 149
[Tue Sep 11 16:18:15.504 2018] 149
[Tue Sep 11 16:18:15.509 2018] 149
[Tue Sep 11 16:18:15.514 2018] 149
[Tue Sep 11 16:18:15.520 2018] 149
[Tue Sep 11 16:18:15.524 2018] 149
[Tue Sep 11 16:18:15.531 2018] 149
[Tue Sep 11 16:18:15.534 2018] 149
[Tue Sep 11 16:18:15.539 2018] 149
[Tue Sep 11 16:18:15.546 2018] 149
[Tue Sep 11 16:18:15.551 2018] 149
[Tue Sep 11 16:18:15.556 2018] 149
[Tue Sep 11 16:18:15.561 2018] 149
[Tue Sep 11 16:18:15.567 2018] 149
[Tue Sep 11 16:18:15.571 2018] 149
[Tue Sep 11 16:18:15.577 2018] 149
[Tue Sep 11 16:18:15.580 2018] 149
[Tue Sep 11 16:18:15.586 2018] 149
[Tue Sep 11 16:18:15.590 2018] 149
[Tue Sep 11 16:18:15.596 2018] 149
[Tue Sep 11 16:18:15.602 2018] 149
[Tue Sep 11 16:18:15.607 2018] 149
[Tue Sep 11 16:18:15.613 2018] 149
[Tue Sep 11 16:18:15.617 2018] 149
[Tue Sep 11 16:18:15.622 2018] 149
[Tue Sep 11 16:18:15.626 2018] 149
[Tue Sep 11 16:18:15.632 2018] 149
[Tue Sep 11 16:18:15.637 2018] 149
[Tue Sep 11 16:18:15.643 2018] 149
[Tue Sep 11 16:18:15.648 2018] 149
[Tue Sep 11 16:18:15.654 2018] 149
[Tue Sep 11 16:18:15.658 2018] 149
[Tue Sep 11 16:18:15.664 2018] 149
[Tue Sep 11 16:18:15.669 2018] 149
[Tue Sep 11 16:18:15.674 2018] 149
[Tue Sep 11 16:18:15.679 2018] 149
[Tue Sep 11 16:18:15.684 2018] 149
[Tue Sep 11 16:18:15.689 2018] 149
[Tue Sep 11 16:18:15.694 2018] 149
[Tue Sep 11 16:18:15.700 2018] 149
[Tue Sep 11 16:18:15.704 2018] 149
[Tue Sep 11 16:18:15.709 2018] 149
[Tue Sep 11 16:18:15.713 2018] 149
[Tue Sep 11 16:18:15.720 2018] 149
[Tue Sep 11 16:18:15.725 2018] 149
[Tue Sep 11 16:18:15.730 2018] 149
[Tue Sep 11 16:18:15.735 2018] 149
[Tue Sep 11 16:18:15.741 2018] 149
[Tue Sep 11 16:18:15.747 2018] 149
[Tue Sep 11 16:18:15.750 2018] 149
[Tue Sep 11 16:18:15.756 2018] 149
[Tue Sep 11 16:18:15.761 2018] 149
[Tue Sep 11 16:18:15.766 2018] 149
[Tue Sep 11 16:18:15.771 2018] 149
[Tue Sep 11 16:18:15.776 2018] 149
[Tue Sep 11 16:18:15.781 2018] 149
[Tue Sep 11 16:18:15.787 2018] 149
[Tue Sep 11 16:18:15.793 2018] 149
[Tue Sep 11 16:18:15.796 2018] 149
[Tue Sep 11 16:18:15.802 2018] 149
[Tue Sep 11 16:18:15.807 2018] 149
[Tue Sep 11 16:18:15.813 2018] 149
[Tue Sep 11 16:18:15.817 2018] 149
[Tue Sep 11 16:18:15.823 2018] 149
[Tue Sep 11 16:18:15.827 2018] 149
[Tue Sep 11 16:18:15.834 2018] 149
[Tue Sep 11 16:18:15.838 2018] 149
[Tue Sep 11 16:18:15.843 2018] 149
[Tue Sep 11 16:18:15.849 2018] 149
[Tue Sep 11 16:18:15.853 2018] 149
[Tue Sep 11 16:18:15.859 2018] 149
[Tue Sep 11 16:18:15.864 2018] 149
[Tue Sep 11 16:18:15.870 2018] 149
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As you can see, the timer never restarts!

 

 

 

I am at a loss on how to proceed.  Sorry for the super-long post, but I feel like I would have had to post all this info anyways in response to questions from the community.

 

Any help would be greatly appreciated!

I love the smell of burning silicon in the morning

Last Edited: Fri. Sep 14, 2018 - 11:31 AM
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Just to clear me head after looking at the above...... When you say RTC I guess you mean a software RTC?

 

Also is the RTC running off the Crystal as in it being 32KHz(frequency not shown) while the processor clock runs from the internal clock?

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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sorry yes it's a 32.768 khz Crystal connected.

the processor runs 8 mhz internal. Prescaler of 128 results in tcnt2 overflow at a frequency of 1 hz

I love the smell of burning silicon in the morning

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jaza_tom wrote:
As you can see, after the prescaler in TCCR2B gets latched, the timer begins incrementing again (it sits at 149 for about 230 ms and then starts incrementing again)   Here is the same output for PCB V2:

 

jaza_tom wrote:
As you can see, the timer never restarts!  
  (always 149)

 

The long lead-in effect is interesting, and shows a common artifact with some prescaler/dividers, in that they reload once they overflow, but that initial path to overflow might be less defined....

some simple sanity checks here would be

 - to run the second test overnight to catch any possible initial path effect...

- actually, not so much a digital effect, there is also the good old fashioned start up time, which can be seconds 

- feed in an external  RTC signal, maybe a PC sound card and a terminator-at-pcb approach.

    You need to generate a low amplitude 8192/16384/32768  Hz  sine, without other signals added. ( but 32768 might not make it thru some sound cards)

    8192 should be ok, but change to square wave to avoid too-slow dV/dT, and then add a cap at the test point, to make dV/dT similar to 32kHz

   So it clocks at 1/4 speed, but otherwise edges are '32k like' 

 

Hmm, I see various changes and a pin6 now routed that was not before ?

Other tests would be to

 Drive pin6 low/hi if that might be floating, during Osc start,

 find a lowest ESR xtal / lowest C you can locate & try that, lowering pcb caps as needed

 can it be persuaded to touch-excite using a scope / meter probe  onto  TOsc1/TOsc2

 

Last Edited: Wed. Sep 12, 2018 - 12:03 AM
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Just along the generic lines of "my system is doing impossible things,"

 

-How many different boards / micro controllers have you tried in the failing configuration?

 

-Also, how much flash and SRAM (especially) is your program using?

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kk6gm wrote:
Just along the generic lines of "my system is doing impossible things,"   -How many different boards / micro controllers have you tried in the failing configuration?

 

heart

 

Thanks for the prodding on this point.  I have a run of 10 boards, and had tested this on 2 of them.  Turns out, these 2/10 boards were the only ones in the batch that had their oscillators solder-bridged.

 

The test program works as expected on the remaining 8/10 boards.

 

blush

 

Sorry if you have gotten to the end of this super-long thread only to find out that it was an assembly related issue.

 

I love the smell of burning silicon in the morning

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Hah!  If you had only tried 1, bad on you.  But having the first 2 fail, not so bad on you for thinking it was some other problem.  Glad it was that simple.

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jaza_tom wrote:
Sorry if you have gotten to the end of this super-long thread only to find out that it was an assembly related issue.
Same old, same old...

Ross McKenzie ValuSoft Melbourne Australia

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I just wasted several minutes looking at your layouts and track/via placement etc.

 

@OP: Please mark thread as solved so others don't waste their time also.