Hello guys, First, I am Korean so my English is some awkward but I will try to my best.
I have been studied for a month after graduation and now I studied at I2C interface & Protocol
and I got a problem with hardware sequence.
If I may ask, I wonder to know Hardware sequences in detail.
After starting I2C communication, slave and master both communicate 8-bit data and 1-bit ack, am I right?
If I am good to understand that let you know about my problem.
First, according to this website (http://www.ermicro.com/blog/?p=1239)
in Master's write mode, at last, sequence point, they got ACK from slave and master sends STOP signal to end hands shake.
But I can't understand at this point, how can the slave distinguish this signal is STOP? OR DATA?
According to this picture, master got Ack from a slave and they go to sequence sending a data.
However, STOP is (SCL 1 / SDA 1) if trailing data would be data is 1, This signal could be (SCL 1 / SDA 1) !?..
Then, the slave can't know this signal is Data or STOP because it is same level 1/1.
How can slave distinguish this as STOP or DATA?
Seconds is Hardware level.
Master's cathing timing is SCL 1. If SCL would be 0, slave or master can change signal.
Then I think, If data signal 1 in SCL 1, I mean both is 1 level.
This condition is a Free state also the delay condition which devices can understand "FreeState" is just 1.3 us or 4.7us and I2c Speed is just 400 kHz ~ 100KHz.
So I guess If that timing, data 1 and SCL 1, another master can interfere with both's communication.
Are my thoughts right?
And I am sorry -_- my English isn't sure