Come Join Us (MPLAB Now Supports AVRs)

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One other development, Microchip’s newly released, low-cost PICkit™ 4 In-Circuit programming and debugging development tool also currently provides Beta support for AVRs.

PICkit 4 is on-sale :

Microchip Direct Logo

microchipDIRECT

DEVELOPMENT TOOL DEALS

https://www.microchipdirect.com/product/DevToolDeals

...

 

Part Number: PG164140 - MPLAB PICkit 4 In-Circuit Debugger 

...

[47.95USD then 20% off]

...

[in stock, 308]

...

 

Edit : zero stock as of 13-Aug'18; IIRC, the sales price is honored when restocked.

Edit1 : restocked at 1366 as of 17-Aug'18

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Sat. Aug 18, 2018 - 04:43 AM
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low-cost PICkit™ 4

It is ... interesting that Microchip has embraced the SAM chips for use in their debuggers.  The nEDBG chip on the recent PIC16F18446 giveaway board is a SAMD21, and this PicKit4 has a SAME70...

Any word on whether PICKit 4 will support ARM chips?  (It should be able to - has SWD and JTAG.  I guess the more correct question is whether Atmel Studio will support PICKit4...)

 

PS: Thanks!  Ordered.  20% discount + free shipping via FLASHSHIP - $38+tax was irresistible.

 

 

More worrisome is the "AVR Support in XC8", given XC8's rather sketchy reputation in "free" mode.   And no C++.

 

 

>>  http://microchipdeveloper.com/mp...

 

Hmm.  There are some problems with that page, I think.   I especially like:

Concept MPLAB Atmel Studio
Set/Clear Bit Values
Clear bit: Bit value = 0
Set bit: Bit value = 1
Clear bit: Bit value = 1
     

They're presumably talking about fuse/config bits.  But I don't think that's obvious, especially if you're new to AVRs.

 

Last Edited: Fri. Aug 3, 2018 - 07:45 AM
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westfw wrote:
It is ... interesting that Microchip has embraced the SAM chips for use in their debuggers. The nEDBG chip on the recent PIC16F18446 giveaway board is a SAMD21, and this PicKit4 has a SAME70...

I presume that that is the same logic as using ATmega32U4 for mEDBG on XMINI boards.    It works but the "performance" is poor.

 

The "paid-for" debuggers will have a proper performance e.g. ATMEL-ICE or PicKit4.

 

It seems to be a crazy marketing decision.    It costs a few cents more to use SAME70 instead of SAMD21.    Likewise UC32 vs AVR.   Prospective customers explore the evaluation/giveaway boards and conclude that the target chips are "worse" than NXP, ST, TI, ...

The only argument for ATmega32U4 is 5V tolerance.    But PicKit hardware have always coped with 5V.

 

David.

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westfw wrote:

More worrisome is the "AVR Support in XC8", given XC8's rather sketchy reputation in "free" mode.

 

An oft repeated claim but one that no-one has ever produced any real-world evidence for, or not that I've ever found. I've seen figures of 10% slower code/more RAM/more Flash but, IMHO, if 10% is the difference between your project working and your project breaking then you have bigger problems.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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westfw wrote:
Any word on whether PICKit 4 will support ARM chips?
SAM S70 and E70 in MPLAB X 5 (first in MPLAB X 4.20) from 'Device Support.htm'.

 

"Dare to be naïve." - Buckminster Fuller

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>> XC8's rather sketchy reputation in "free" mode.

An oft repeated claim but one that no-one has ever produced any real-world evidence for, or not that I've ever found.

 Oh, there was plenty of evidence when XC8 first came out; much discussion on the PICList mailing list.

Things were improved quite a bit since then, and the hard part is figuring out whether a given bit of source code is going to fall into the "adequately optimized" column, or the "you've got to be kidding" column.

 

Most recently (last week or so) there was a blog post ( https://www.bitsnblobs.com/blog/... ) where it was reported that the PIC16F18446 board (mentioned previously) ran a "native" pin-toggle benchmark at about the same speed as an Arduino digitalWrite() loop (at the same clockspeed.)  Now, at the same clockspeed, a PIC is about 4x slower than an AVR.  But digitalWrite() in Arduino is 10 to 20x slower than "native" code, so the PIC *should* have come out ahead by quite a bit.

 

I investigated.   I had a PIC16F18855 board, and it's "hello world" LED blink code ran significantly faster.   Initially, I expected errors in clock configuration.

But it turns out that the current Microchip Code Configurator tool generates nice macros for pin toggle:

#define IO_RA2_Toggle() do { LATAbits.LATA2 = ~LATAbits.LATA2; } while(0);

While the (older?) example I had for the 18855 had:

#define IO_RA0_Toggle()   do { LATA0 = ~LATA0; } while(0)

 

Those should be about equivalent, right?  All compile-time constant folding, essentially?

 

Nope.   The later (older) example produces "reasonable" code:

0x26: MOVLW 0x4
0x27: MOVLB 0x0
0x28: XORWF LATA, F
0x29: GOTO 0x26

It could short-circuit that loop a bit more (GOTO 28 instead of GOTO 26), but ... good enough.

 

The newer-style code, however, produced:

!      do { LATAbits.LATA2 = ~LATAbits.LATA2; } while(0);
0x26: BCF STATUS, 0x0
0x27: MOVLB 0x0
0x28: BTFSS LATA, 0x2
0x29: BSF STATUS, 0x0
0x2A: BTFSC STATUS, 0x0
0x2B: GOTO 0x2D
0x2C: GOTO 0x30
0x2D: MOVLB 0x0
0x2E: BSF LATA, 0x2
0x2F: GOTO 0x32
0x30: MOVLB 0x0
0x31: BCF LATA, 0x2
0x32: GOTO 0x26

Someone else confirmed that the "Pro" compiler with optimization settings (unusable to free users) does optimize the new-style source to the same as the old-style source.

 

XC16 and XC32 are gcc-based, but don't allow the usual gcc optimization flags.  The net is rife with instructions on how to patch the binaries, and/or environment, and/or compile from source, since all those options are supposedly legal according to the gcc licenses...  (however, gcc with -O0 is not nearly as bad as the original XC8.   We were expecting code like -O0, and we got ... the sort of code you'd expect out of someone's 2nd year compiler project, in which the main point was to learn about parsing...)

 

 

[SAMD21 or ATmega32u4 instead of SAME70] works but the "performance" is poor.

The sad part is that I really don't see any reason that a SAMD21, or even a 32u4, should have "poor" performance for this sort of application.

If the Xplained Mini boards weren't so cheap, *I'd* be working on a faster version.   Maybe.  At least to the extent of figuring out whether CMSIS/DAP introduces unavoidable overhead.

 

Last Edited: Fri. Aug 3, 2018 - 10:34 PM
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SAMD21 is Cortex-M0 @ 48MHz.    Considerably poorer performance than M3 or M4 @ 48MHz.   And obviously noticeably slower than M4, M7 @ 200MHz or faster.

 

Mega32U4 @ 16MHz is severely limited for Flash as well as speed.     I suspect that the worst bottlenecks could be "improved" but you are still stuck for speed.    DebugWIRE is inherently slower than SWD or UPDI but it should not be that SLOW.

 

Hey-ho.   The XMINI-328P does work.   So it is better than nothing.

 

David.

 

 

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Yes, but doing something simple like programming the flash ought to be limited by either the uplink speed to the PC (full speed USB for both of those chips, right?) or the downlink speed to the chip (which shouldn't change between debug technology.)  And yes, "32k" is "Severely limited flash" in some sense. but I'd think it would be plenty for any single target (granted, if you have an mEDBG chip, and it's supposed to support everything, then that's a valid excuse for code space issues...

 

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To whom it may concern... finally, someone was able to direct me to the PICKIT4->AVR pin mapping, and I can confirm programming an ATmega4809 (UPDI interface) with the PICKIT4 from MPLAB X IDE 5.00.

Here's the link: http://microchipdeveloper.com/pi...

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@westfw wrote:

More worrisome is the "AVR Support in XC8", given XC8's rather sketchy reputation in "free" mode.   And no C++.

There is no requirement to use the XC8 compiler for AVRs in MPLABX.  The AVR toolchain has worked for me on both Windows or Linux.

 

Greg Muth

Portland, OR, US

Xplained/Pro/Mini Boards mostly

 

Make Xmega Great Again!

 

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I was hoping they would add PIC support to AtmelICE. The Microchip programmers are awful, especially the ICD range.

 

I just hope the free toolchain is maintained.

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YouTube

Getting Started - AVR® in MPLAB® X - Ep. 1 - Import Studio 7 Project into MPLAB X IDE

Microchip Technology

Aug 7, 2018

https://www.youtube.com/watch?v=uMOKiY3bdjM (3m44s)

Example import:

• ASF3 Example Project

 

Import process:

• Locate Studio *.cproj File

• Select Device

• Select Tool

• Select Compiler

• Name project & folder

 

How import works:

• Source files linked (not copied)

[2 URL]

via https://plus.google.com/+MicrochipTech/posts/ZBBSkLo3sU5

 

Edit: browse YouTube Microchip Technology for two more videos in that series

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Mon. Aug 13, 2018 - 09:47 PM
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david.prentice wrote:

I presume that that is the same logic as using ATmega32U4 for mEDBG on XMINI boards.    It works but the "performance" is poor.

 

The "paid-for" debuggers will have a proper performance e.g. ATMEL-ICE or PicKit4.

 

It seems to be a crazy marketing decision.    It costs a few cents more to use SAME70 instead of SAMD21.    Likewise UC32 vs AVR.   Prospective customers explore the evaluation/giveaway boards and conclude that the target chips are "worse" than NXP, ST, TI, ...

I agree better is always good, but 'a few cents more' is not quite accurate :

ATSAMD21E15L 32QFN  $0.735/3k

cheapest SAME70

ATSAME70J19A-AN   64LQFP  $7.19970/3k

 

 

There is a ATSAM3U1CB-AU, with 480MHz HS-USB, for $2.44/1k, but they seem to have skipped over that ?  Maybe it has some issues ?  Or was the 512k / 300MHz of the SAME70 seen as more future proof ?

 

 

A key increment here seems to be the jump from FS-USB to HS-USB, ( as well as a core MCU MHz jump that would allow even an intern code useful speed.)

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What price they can sell a chip on the open market is not relevant to the manufacturer.

 

They only have to consider the die size and wafer yield.     There is no need to go for the ultimate performance but their brand name tools deserve to work well and with some future proofing.

 

It is less clear with a "giveaway" evaluation board.    Do you go for cheap or "adequate"?

Personally,   I think that the mEDBG was a false economy.     Just compare the Microchip/Atmel evaluation boards with ST, TI, SiLabs, ...

 

David.

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gchapman wrote:

YouTube

Getting Started - AVR® in MPLAB® X - Ep. 1 - Import Studio 7 Project into MPLAB X IDE

Microchip Technology

Aug 7, 2018

https://www.youtube.com/watch?v=uMOKiY3bdjM (3m44s)

Example import:

• ASF3 Example Project

 

Import process:

• Locate Studio *.cproj File

• Select Device

• Select Tool

• Select Compiler

• Name project & folder

 

How import works:

• Source files linked (not copied)

[2 URL]

via https://plus.google.com/+MicrochipTech/posts/ZBBSkLo3sU5

 

Edit: browse YouTube Microchip Technology for two more videos in that series

 

 

Thanks, that was interesting. It seems to work well enough for a simple ASF project. I'm going to try it.

 

I think Atmel Studio is dead now. MPLAB is inferior but we will have to get used to it, because AS7 will be the last version.

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mojo-chan wrote:
I think Atmel Studio is dead now.

You will still be able to keep using it; it just won't get updated.

 

After all, people are still using WinAVR, and ancient versions of AVR Studio - long after they were "discontinued" ... !

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...
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awneil wrote:

mojo-chan wrote:
I think Atmel Studio is dead now.

You will still be able to keep using it; it just won't get updated.

 

After all, people are still using WinAVR, and ancient versions of AVR Studio - long after they were "discontinued" ... !

 

As long as they keep updating for new parts I suppose. But yes, I won't bother upgrading projects for the most part, just start from scratch. I tend not to upgrade production code unless there is a very good reason.

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mojo-chan wrote:
As long as they keep updating for new parts I suppose.

Well, that's the point: they probably won't - so it'll be frozen in time; it'll just carry on doing what it does now.

 

And there's also talk that Microchip won't be updating avr-gcc ...

 

EDIT

 

Here: #108

 

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...
Last Edited: Tue. Aug 14, 2018 - 09:58 AM
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awneil wrote:
And there's also talk that Microchip won't be updating avr-gcc ...

 

That would be a real blow to the maker and open source communities. Arduino, for example, picked AVR in no small part because there is a free high quality compiler for it.

 

Maybe it's time to think about ditching Microchip/Atmel architectures and moving to ARM. At least then you are not tied to one manufacturer's mast and gcc will always be free and up to date.

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Maybe Arduino has gained a sufficient "critical mass" to be able to keep avr-gcc going independently ... ?

 

Or maybe they will adopt the same strategy: freeze all the AVR stuff as it is now, and everything new happens on ARM ... ?

 

After all, there's now quite a few non-AVR Arduinos  - particularly ARM  ...

 

EDIT

 

On the discontinuation of avr-gcc: #108

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...
Last Edited: Tue. Aug 14, 2018 - 09:59 AM
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westfw wrote:
Someone else confirmed that the "Pro" compiler with optimization settings (unusable to free users) does optimize the new-style source to the same as the old-style source.

 

Sad news. Looks like they decided to steal our free software, gimp it and make building the legally required release of the optimized version extremely difficult and time consuming.

 

Just think of the effort they had to put in to destroying the free version's performance, and how it could have been better spent on something productive.

 

Whatever good will Atmel had is quickly being destroyed. Microchip can shove their compiler, and forget about me designing their parts into new products. What made Atmel so great was the community, and respecting the GPL and having a decent free compiler are core requirements. I'm not going to contribute my time and energy if they take but give nothing back.

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awneil wrote:
Maybe Arduino has gained a sufficient "critical mass" to be able to keep avr-gcc going independently ... ?
Likely yes and Microchip has a link to Arduino through Bob Martin.

This post was updated today :

https://www.avrfreaks.net/forum/come-join-us-mplab-now-supports-avrs?page=2#comment-2504476

 

A while back, one of the Arduino creators asked the Arduino community to merge the Atmel AVR GCC patches into the Arduino AVR toolchain (it was done)

Assuming the ones at Microchip release what they can of xc8-gcc then it'll get done again.

One advantage of AVR in Microchip's 8-bit line-of-business is C++.

 


http://www.microchip.com/development-tools/maker-diy-solutions

 

"Dare to be naïve." - Buckminster Fuller

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mojo-chan wrote:
MPLAB is inferior but we will have to get used to it, because AS7 will be the last version.
A door has opened to third parties.

Microsoft Visual Studio AVR extensions though not zero price (low price) and incomplete AVR model coverage :

  • PlatformIO
  • VisualGDB

 

Zero price is the current EDBG in Microsoft Visual Studio Code though some effort to add AVR to it and it's more akin to AVR Studio than Atmel Studio :

https://www.avrfreaks.net/forum/avr-studio-mac-linux#comment-2440271

 

Long poles in the tent :

  • lifetime of EDBG
  • third party support of MPLAB PICkit 4 and MPLAB ICD 4

 


http://docs.platformio.org/en/latest/ide/visualstudio.html

PlatformIO value-added (iow not zero price) for arm, ESP32, RISC-V, and Texas Instruments MSP430 :

http://docs.platformio.org/en/latest/plus/debugging.html

PlatformIO AVR EDBG :

PIO Unified Debugger for AVR · Issue #95 · platformio/platform-atmelavr · GitHub

https://github.com/platformio/platform-atmelavr/issues/95

can Ivan be convinced to add EDBG?

reason: VisualGDB is a GDB client

https://visualgdb.com/tutorials/avr/

 

"Dare to be naïve." - Buckminster Fuller

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Does anyone have a link to the Microchip compiler source archives? I'm tempted to set up a build environment and release free versions periodically.

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Microchip Technology Inc

Microchip Technology

PIC and dsPIC Downloads Archive

http://www.microchip.com/development-tools/pic-and-dspic-downloads-archive

(near bottom)

Source Archives

"Dare to be naïve." - Buckminster Fuller

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"Dare to be naïve." - Buckminster Fuller

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FSF AVR GCC on Windows :

AVR-GCC 8.1.0 for Windows 32 and 64 bit

By 

http://blog.zakkemble.co.uk/avr-gcc-builds/

due to https://gcc.gnu.org/

 

Edit : one AVR regression fixed in 8.2 : https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85805

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Tue. Aug 14, 2018 - 02:33 PM
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I think I speak for quite a few part-timers and people who just screw around with this stuff in our spare time: We don't like to feel like we are missing out on the tools. Paying for MPLAB isn't really in the cards for someone like me, and if I'm using the free version and constantly feel like I'm missing out, it isn't going to make me happy. It is going to make me look for a different toolchain, possibly one for different chips with a company who is more interested in selling chips instead of tools.

 

So what you say, you guys only buy a few chips! Ah, well, yes. But we improve the ecosystem, build libraries and give them away, test and popularize things and ultimately make things easier for everyone. That million item product down the road may well use a particular chip because of some home gamer like me. And, often, might even be made by a home gamer like me.

 

Microchip needs to drag themselves out of the dark ages of nickel and dimeing their engineers/devs and decide if they want to sell chips or tools. They could also help their case by teaming up more; I'd be happy if they provided a tool chain for something like CLion (with hardware debugging) or others.

 

 

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gchapman wrote:

Microchip Technology Inc

Microchip Technology

PIC and dsPIC Downloads Archive

http://www.microchip.com/development-tools/pic-and-dspic-downloads-archive

(near bottom)

Source Archives

 

Thanks, but I searched the whole page for "XC8" but the only mention of it is the binary installer. Maybe I'll email them.

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Mr.Paul wrote:
Paying for MPLAB ...
/pedantic on

MPLAB XC

/pedantic off

wink

Having a zero price IDE (MPLAB X) is ecosystem essential with today's competitors.

Mr.Paul wrote:
They could also help their case by teaming up more; ...
Atmel did not compete against third parties.

Microchip does compete against third parties (HP InfoTech, Imagecraft, IAR)

xc8-gcc vs (CodeVisionAVR, JumpStart C for AVR, EWAVR)

Mr.Paul wrote:
I'd be happy if they provided a tool chain for something like CLion (with hardware debugging) or others.
I emphatically second your motion!!!!

An example of such is Texas Instruments packages and maintains FSF MSP430 GCC and has a multi-platform debugger interface package in MSPDS.

Advantage AVR is some megaAVR and XMEGA AVR have an EBI (MSP430 doesn't have an EBI)

Another AVR advantage is an extended temperature range though TI has recently added several 105C to the MSP430 line and has several at 125C or greater.

 


http://hpinfotech.ro/

http://imagecraft.com/

https://www.iar.com/iar-embedded-workbench/#!?architecture=AVR

http://www.ti.com/tool/msp430-gcc-opensource

http://www.ti.com/tool/MSPDS

 

"Dare to be naïve." - Buckminster Fuller

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Mr.Paul wrote:

...and if I'm using the free version and constantly feel like I'm missing out, it isn't going to make me happy.

 

But does lacking a few percent of optimisation really matter?

 

You buy a mega328 and you don't spend your time anguishing over why Atmel didn't make it with 64k of flash do you?

You buy a new car and you don't waste time wishing it did 130MPH instead of 120MPH do you?

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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Looks like they decided to steal our free software, gimp it and make building the legally required release of the optimized version extremely difficult and time consuming.

To be fair, XC8 is not based on "free software" of any sort.  XC16 and XC32 are built on gcc, and instructions for building those (or otherwise removing the optimization restrictions) are widely available.

 

The Microchip compilers do not include C++ for the 8bit CPUs, which is a pretty substantial problem, given both Arduino, and a large contingent of "it's time for the embedded world to consider using C++" prophets and evangelists.

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Mr.Paul wrote:

...and if I'm using the free version and constantly feel like I'm missing out, it isn't going to make me happy.

 

But does lacking a few percent of optimisation really matter?

 

That is entirely missing the point. It will all be "ok, you want to do X, that is only available in the pro version" and "Oh, your loop is sloppy, that is only available in the pro version", etc. What I want to focus on is programming the chip. I don't want to drop hundreds or thousands on an IDE, and all the oh you need the update but your maintenance is not up to date. I want the best the company has to offer, so that I don't have to think about "Should I upgrade my IDE" instead can think "How can I keep this wake up and poll sequence under 4ms", which is a vastly more fun problem to solve.

 

And, for the record, if Atmel had 64k flash in a chip and decided I need to pay an extra free to unlock it, I would not buy that chip. They are, of course, within their rights to that business model, but for personal use I'm not interested in participating. Same for my car; If I bought it and Honda went and said "Oh, you know, that car will do 130 mph, just subscribe to the fast car program" I not only wouldn't pay, I would be pretty unhappy, even if I didn't plan to do 130 mph.

 

Work is work, commerce is commerce, but when I do things for fun I like it to be friendlier, easier and with less friction (which a paid IDE definitely introduces). It isn't rational from a economics point of view, but fun is fun and profit is profit. Atmel walked that line very wel, microchip is not -- so far -- looking like they are walking well.

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Mr.Paul wrote:

And, for the record, if Atmel had 64k flash in a chip and decided I need to pay an extra free to unlock it, I would not buy that chip.

 

Hehe, but you probably already are doing exactly that.

All those MCU parts with differing code-sizes, but same peripherals & pinouts are usually not differing die - they are the same die, with varying factory options.

Code size is the most easily 'factory set'.

 

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Well yah but I don’t want it in my face. Also the smaller sizes QA better

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As in if you manufacture 64k but only sell 32 and have a fusable page map or something you can get better yield.

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Mr.Paul wrote:
I don't want to drop hundreds or thousands on an IDE, and all the oh you need the update but your maintenance is not up to date.
fyi, MPLAB XC8 Pro in dongle form is a perpetual license and it was on sale last month.

MPLAB XC8 Pro's price would be steep for the small in SMB but likely not a large issue for the medium in SMB; for a large business it's a tool at a reasonable price so maybe it's a good value if its quality is good.

Mr.Paul wrote:
Atmel walked that line very wel, ...
Concur

Mr.Paul wrote:
... microchip is not -- so far -- looking like they are walking well.
Compilers as profit centers.

Continual pressure on profit centers is likely the Microchip way; investors and shareholders like that.

Transparency - I do not possess any Microchip stock.

Reason - twice bitten, thrice shy (dotcom bust, Oct'08)

Lesson learned - support Main Street, not Wall Street

Matters not ... why?

WinAVR is dead ... long live WinAVR

wink

AVR's ecosystem is well past critical mass (an amazing number of computer languages and compilers or interpreters)

My concern is with debuggers.

Is EDBG a part of MPLAB PICkit 4?

 


https://www.avrfreaks.net/forum/come-join-us-mplab-now-supports-avrs?page=2#comment-2504076

 

"Dare to be naïve." - Buckminster Fuller

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But does lacking a few percent of optimisation really matter?

No.  But the example I quoted recently ( https://www.avrfreaks.net/commen... ) was more than 3x bigger (13 words instead of 4), and much slower (3.4us vs 1.3us) than the "obvious" object code.  Various other folks have mentioned that "example projects" fail to fit in the target chip when compiled with the free version of the compiler.  Those are problems worth complaining about.  When I look at the object code produced by the compiler, I should be able to say "Well, I could have done it faster if I tried", but not "This is stupid!"

 

In a way, I have similar objections to ASF.  1k of initialization code for the system clock is sort-of OK on a SAMD21 with 256k of flash, but it's not really acceptable for the SAMD09 with 8k...

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One of the best things about Atmel parts is the community support. If you go over the Microchip forums you will see a night and day difference. No real community, people don't volunteer their time like they do here. Microchip has to pay staff to answer questions.

 

If Microchip destroy that just because they insist on charging for the compiler then people will move on to something else.

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Brian Fairchild wrote:
You buy a new car and you don't waste time wishing it did 130MPH instead of 120MPH do you?
Err, speak for yourself! (top speed may not matter per se but it's a likely indication of aerodynamics and engine power which DO matter!)

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clawson wrote:

Brian Fairchild wrote:
You buy a new car and you don't waste time wishing it did 130MPH instead of 120MPH do you?
Err, speak for yourself! (top speed may not matter per se but it's a likely indication of aerodynamics and engine power which DO matter!)

 

Ah, but you bought that car knowing that the brochure said 120.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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I would never buy a car if the brochure only said 120 !!

 

Seriously though, the difference between optimisation and none can be a whole lot more than +5..10%. Here's an example using a very simple code from another thread...

D:\atmel_avr\avr8-gnu-toolchain-win32_x86\bin>type avr.c
#define F_CPU 1000000UL
#include <avr/io.h>
#include <util/delay.h>

int main(void) {
    DDRB = 0xFF;
    DDRC = 0xFF;
    DDRD = 0xFF;
    while(1) {
        PORTB ^= 0xFF;
        PORTC ^= 0xFF;
        PORTD ^= 0xFF;
        _delay_ms(100);
    }
}

D:\atmel_avr\avr8-gnu-toolchain-win32_x86\bin>avr-gcc -mmcu=atmega328p -O0 -g avr.c -o avr.elf
In file included from avr.c:3:0:
d:\atmel_avr\avr8-gnu-toolchain-win32_x86\avr\include\util\delay.h:112:3: warning: #warning "Compiler optimizations disabled; functions from <util/del
ay.h> won't work as designed" [-Wcpp]
 # warning "Compiler optimizations disabled; functions from <util/delay.h> won't work as designed"
   ^

D:\atmel_avr\avr8-gnu-toolchain-win32_x86\bin>avr-objdump -S avr.elf

avr.elf:     file format elf32-avr

Disassembly of section .text:

00000000 <__vectors>:
   0:   0c 94 34 00     jmp     0x68    ; 0x68 <__ctors_end>
   4:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
   8:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
   c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  10:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  14:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  18:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  1c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  20:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  24:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  28:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  2c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  30:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  34:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  38:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  3c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  40:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  44:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  48:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  4c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  50:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  54:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  58:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  5c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  60:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  64:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>

00000068 <__ctors_end>:
  68:   11 24           eor     r1, r1
  6a:   1f be           out     0x3f, r1        ; 63
  6c:   cf ef           ldi     r28, 0xFF       ; 255
  6e:   d8 e0           ldi     r29, 0x08       ; 8
  70:   de bf           out     0x3e, r29       ; 62
  72:   cd bf           out     0x3d, r28       ; 61
  74:   0e 94 40 00     call    0x80    ; 0x80 <main>
  78:   0c 94 02 02     jmp     0x404   ; 0x404 <_exit>

0000007c <__bad_interrupt>:
  7c:   0c 94 00 00     jmp     0       ; 0x0 <__vectors>

00000080 <main>:
#define F_CPU 1000000UL
#include <avr/io.h>
#include <util/delay.h>

int main(void) {
  80:   cf 93           push    r28
  82:   df 93           push    r29
  84:   cd b7           in      r28, 0x3d       ; 61
  86:   de b7           in      r29, 0x3e       ; 62
  88:   2e 97           sbiw    r28, 0x0e       ; 14
  8a:   0f b6           in      r0, 0x3f        ; 63
  8c:   f8 94           cli
  8e:   de bf           out     0x3e, r29       ; 62
  90:   0f be           out     0x3f, r0        ; 63
  92:   cd bf           out     0x3d, r28       ; 61
    DDRB = 0xFF;
  94:   84 e2           ldi     r24, 0x24       ; 36
  96:   90 e0           ldi     r25, 0x00       ; 0
  98:   2f ef           ldi     r18, 0xFF       ; 255
  9a:   fc 01           movw    r30, r24
  9c:   20 83           st      Z, r18
    DDRC = 0xFF;
  9e:   87 e2           ldi     r24, 0x27       ; 39
  a0:   90 e0           ldi     r25, 0x00       ; 0
  a2:   2f ef           ldi     r18, 0xFF       ; 255
  a4:   fc 01           movw    r30, r24
  a6:   20 83           st      Z, r18
    DDRD = 0xFF;
  a8:   8a e2           ldi     r24, 0x2A       ; 42
  aa:   90 e0           ldi     r25, 0x00       ; 0
  ac:   2f ef           ldi     r18, 0xFF       ; 255
  ae:   fc 01           movw    r30, r24
  b0:   20 83           st      Z, r18
    while(1) {
        PORTB ^= 0xFF;
  b2:   85 e2           ldi     r24, 0x25       ; 37
  b4:   90 e0           ldi     r25, 0x00       ; 0
  b6:   25 e2           ldi     r18, 0x25       ; 37
  b8:   30 e0           ldi     r19, 0x00       ; 0
  ba:   f9 01           movw    r30, r18
  bc:   20 81           ld      r18, Z
  be:   20 95           com     r18
  c0:   fc 01           movw    r30, r24
  c2:   20 83           st      Z, r18
        PORTC ^= 0xFF;
  c4:   88 e2           ldi     r24, 0x28       ; 40
  c6:   90 e0           ldi     r25, 0x00       ; 0
  c8:   28 e2           ldi     r18, 0x28       ; 40
  ca:   30 e0           ldi     r19, 0x00       ; 0
  cc:   f9 01           movw    r30, r18
  ce:   20 81           ld      r18, Z
  d0:   20 95           com     r18
  d2:   fc 01           movw    r30, r24
  d4:   20 83           st      Z, r18
        PORTD ^= 0xFF;
  d6:   8b e2           ldi     r24, 0x2B       ; 43
  d8:   90 e0           ldi     r25, 0x00       ; 0
  da:   2b e2           ldi     r18, 0x2B       ; 43
  dc:   30 e0           ldi     r19, 0x00       ; 0
  de:   f9 01           movw    r30, r18
  e0:   20 81           ld      r18, Z
  e2:   20 95           com     r18
  e4:   fc 01           movw    r30, r24
  e6:   20 83           st      Z, r18
  e8:   80 e0           ldi     r24, 0x00       ; 0
  ea:   90 e0           ldi     r25, 0x00       ; 0
  ec:   a8 ec           ldi     r26, 0xC8       ; 200
  ee:   b2 e4           ldi     r27, 0x42       ; 66
  f0:   89 83           std     Y+1, r24        ; 0x01
  f2:   9a 83           std     Y+2, r25        ; 0x02
  f4:   ab 83           std     Y+3, r26        ; 0x03
  f6:   bc 83           std     Y+4, r27        ; 0x04

        __builtin_avr_delay_cycles(__ticks_dc);

#else
        uint16_t __ticks;
        __tmp = ((F_CPU) / 4e3) * __ms;
  f8:   20 e0           ldi     r18, 0x00       ; 0
  fa:   30 e0           ldi     r19, 0x00       ; 0
  fc:   4a e7           ldi     r20, 0x7A       ; 122
  fe:   53 e4           ldi     r21, 0x43       ; 67
 100:   69 81           ldd     r22, Y+1        ; 0x01
 102:   7a 81           ldd     r23, Y+2        ; 0x02
 104:   8b 81           ldd     r24, Y+3        ; 0x03
 106:   9c 81           ldd     r25, Y+4        ; 0x04
 108:   0e 94 6d 01     call    0x2da   ; 0x2da <__mulsf3>
 10c:   dc 01           movw    r26, r24
 10e:   cb 01           movw    r24, r22
 110:   8d 83           std     Y+5, r24        ; 0x05
 112:   9e 83           std     Y+6, r25        ; 0x06
 114:   af 83           std     Y+7, r26        ; 0x07
 116:   b8 87           std     Y+8, r27        ; 0x08
        if (__tmp < 1.0)
 118:   20 e0           ldi     r18, 0x00       ; 0
 11a:   30 e0           ldi     r19, 0x00       ; 0
 11c:   40 e8           ldi     r20, 0x80       ; 128
 11e:   5f e3           ldi     r21, 0x3F       ; 63
 120:   6d 81           ldd     r22, Y+5        ; 0x05
 122:   7e 81           ldd     r23, Y+6        ; 0x06
 124:   8f 81           ldd     r24, Y+7        ; 0x07
 126:   98 85           ldd     r25, Y+8        ; 0x08
 128:   0e 94 e7 00     call    0x1ce   ; 0x1ce <__cmpsf2>
 12c:   88 23           and     r24, r24
 12e:   2c f4           brge    .+10            ; 0x13a <main+0xba>
                __ticks = 1;
 130:   81 e0           ldi     r24, 0x01       ; 1
 132:   90 e0           ldi     r25, 0x00       ; 0
 134:   9a 87           std     Y+10, r25       ; 0x0a
 136:   89 87           std     Y+9, r24        ; 0x09
 138:   3f c0           rjmp    .+126           ; 0x1b8 <main+0x138>
        else if (__tmp > 65535)
 13a:   20 e0           ldi     r18, 0x00       ; 0
 13c:   3f ef           ldi     r19, 0xFF       ; 255
 13e:   4f e7           ldi     r20, 0x7F       ; 127
 140:   57 e4           ldi     r21, 0x47       ; 71
 142:   6d 81           ldd     r22, Y+5        ; 0x05
 144:   7e 81           ldd     r23, Y+6        ; 0x06
 146:   8f 81           ldd     r24, Y+7        ; 0x07
 148:   98 85           ldd     r25, Y+8        ; 0x08
 14a:   0e 94 68 01     call    0x2d0   ; 0x2d0 <__gesf2>
 14e:   18 16           cp      r1, r24
 150:   4c f5           brge    .+82            ; 0x1a4 <main+0x124>
        {
                //      __ticks = requested delay in 1/10 ms
                __ticks = (uint16_t) (__ms * 10.0);
 152:   20 e0           ldi     r18, 0x00       ; 0
 154:   30 e0           ldi     r19, 0x00       ; 0
 156:   40 e2           ldi     r20, 0x20       ; 32
 158:   51 e4           ldi     r21, 0x41       ; 65
 15a:   69 81           ldd     r22, Y+1        ; 0x01
 15c:   7a 81           ldd     r23, Y+2        ; 0x02
 15e:   8b 81           ldd     r24, Y+3        ; 0x03
 160:   9c 81           ldd     r25, Y+4        ; 0x04
 162:   0e 94 6d 01     call    0x2da   ; 0x2da <__mulsf3>
 166:   dc 01           movw    r26, r24
 168:   cb 01           movw    r24, r22
 16a:   bc 01           movw    r22, r24
 16c:   cd 01           movw    r24, r26
 16e:   0e 94 ec 00     call    0x1d8   ; 0x1d8 <__fixunssfsi>
 172:   dc 01           movw    r26, r24
 174:   cb 01           movw    r24, r22
 176:   9a 87           std     Y+10, r25       ; 0x0a
 178:   89 87           std     Y+9, r24        ; 0x09
 17a:   0f c0           rjmp    .+30            ; 0x19a <main+0x11a>
 17c:   89 e1           ldi     r24, 0x19       ; 25
 17e:   90 e0           ldi     r25, 0x00       ; 0
 180:   9c 87           std     Y+12, r25       ; 0x0c
 182:   8b 87           std     Y+11, r24       ; 0x0b
    milliseconds can be achieved.
 */
void
_delay_loop_2(uint16_t __count)
{
        __asm__ volatile (
 184:   8b 85           ldd     r24, Y+11       ; 0x0b
 186:   9c 85           ldd     r25, Y+12       ; 0x0c
 188:   01 97           sbiw    r24, 0x01       ; 1
 18a:   f1 f7           brne    .-4             ; 0x188 <main+0x108>
 18c:   9c 87           std     Y+12, r25       ; 0x0c
 18e:   8b 87           std     Y+11, r24       ; 0x0b
                while(__ticks)
                {
                        // wait 1/10 ms
                        _delay_loop_2(((F_CPU) / 4e3) / 10);
                        __ticks --;
 190:   89 85           ldd     r24, Y+9        ; 0x09
 192:   9a 85           ldd     r25, Y+10       ; 0x0a
 194:   01 97           sbiw    r24, 0x01       ; 1
 196:   9a 87           std     Y+10, r25       ; 0x0a
 198:   89 87           std     Y+9, r24        ; 0x09
                __ticks = 1;
        else if (__tmp > 65535)
        {
                //      __ticks = requested delay in 1/10 ms
                __ticks = (uint16_t) (__ms * 10.0);
                while(__ticks)
 19a:   89 85           ldd     r24, Y+9        ; 0x09
 19c:   9a 85           ldd     r25, Y+10       ; 0x0a
 19e:   89 2b           or      r24, r25
 1a0:   69 f7           brne    .-38            ; 0x17c <main+0xfc>
 1a2:   14 c0           rjmp    .+40            ; 0x1cc <main+0x14c>
                        __ticks --;
                }
                return;
        }
        else
                __ticks = (uint16_t)__tmp;
 1a4:   6d 81           ldd     r22, Y+5        ; 0x05
 1a6:   7e 81           ldd     r23, Y+6        ; 0x06
 1a8:   8f 81           ldd     r24, Y+7        ; 0x07
 1aa:   98 85           ldd     r25, Y+8        ; 0x08
 1ac:   0e 94 ec 00     call    0x1d8   ; 0x1d8 <__fixunssfsi>
 1b0:   dc 01           movw    r26, r24
 1b2:   cb 01           movw    r24, r22
 1b4:   9a 87           std     Y+10, r25       ; 0x0a
 1b6:   89 87           std     Y+9, r24        ; 0x09
 1b8:   89 85           ldd     r24, Y+9        ; 0x09
 1ba:   9a 85           ldd     r25, Y+10       ; 0x0a
 1bc:   9e 87           std     Y+14, r25       ; 0x0e
 1be:   8d 87           std     Y+13, r24       ; 0x0d
 1c0:   8d 85           ldd     r24, Y+13       ; 0x0d
 1c2:   9e 85           ldd     r25, Y+14       ; 0x0e
 1c4:   01 97           sbiw    r24, 0x01       ; 1
 1c6:   f1 f7           brne    .-4             ; 0x1c4 <main+0x144>
 1c8:   9e 87           std     Y+14, r25       ; 0x0e
 1ca:   8d 87           std     Y+13, r24       ; 0x0d
        _delay_ms(100);
    }
 1cc:   72 cf           rjmp    .-284           ; 0xb2 <main+0x32>

000001ce <__cmpsf2>:
 1ce:   0e 94 1b 01     call    0x236   ; 0x236 <__fp_cmp>
 1d2:   08 f4           brcc    .+2             ; 0x1d6 <__cmpsf2+0x8>
 1d4:   81 e0           ldi     r24, 0x01       ; 1
 1d6:   08 95           ret

000001d8 <__fixunssfsi>:
 1d8:   0e 94 47 01     call    0x28e   ; 0x28e <__fp_splitA>
 1dc:   88 f0           brcs    .+34            ; 0x200 <__fixunssfsi+0x28>
 1de:   9f 57           subi    r25, 0x7F       ; 127
 1e0:   98 f0           brcs    .+38            ; 0x208 <__fixunssfsi+0x30>
 1e2:   b9 2f           mov     r27, r25
 1e4:   99 27           eor     r25, r25
 1e6:   b7 51           subi    r27, 0x17       ; 23
 1e8:   b0 f0           brcs    .+44            ; 0x216 <__fixunssfsi+0x3e>
 1ea:   e1 f0           breq    .+56            ; 0x224 <__fixunssfsi+0x4c>
 1ec:   66 0f           add     r22, r22
 1ee:   77 1f           adc     r23, r23
 1f0:   88 1f           adc     r24, r24
 1f2:   99 1f           adc     r25, r25
 1f4:   1a f0           brmi    .+6             ; 0x1fc <__fixunssfsi+0x24>
 1f6:   ba 95           dec     r27
 1f8:   c9 f7           brne    .-14            ; 0x1ec <__fixunssfsi+0x14>
 1fa:   14 c0           rjmp    .+40            ; 0x224 <__fixunssfsi+0x4c>
 1fc:   b1 30           cpi     r27, 0x01       ; 1
 1fe:   91 f0           breq    .+36            ; 0x224 <__fixunssfsi+0x4c>
 200:   0e 94 61 01     call    0x2c2   ; 0x2c2 <__fp_zero>
 204:   b1 e0           ldi     r27, 0x01       ; 1
 206:   08 95           ret
 208:   0c 94 61 01     jmp     0x2c2   ; 0x2c2 <__fp_zero>
 20c:   67 2f           mov     r22, r23
 20e:   78 2f           mov     r23, r24
 210:   88 27           eor     r24, r24
 212:   b8 5f           subi    r27, 0xF8       ; 248
 214:   39 f0           breq    .+14            ; 0x224 <__fixunssfsi+0x4c>
 216:   b9 3f           cpi     r27, 0xF9       ; 249
 218:   cc f3           brlt    .-14            ; 0x20c <__fixunssfsi+0x34>
 21a:   86 95           lsr     r24
 21c:   77 95           ror     r23
 21e:   67 95           ror     r22
 220:   b3 95           inc     r27
 222:   d9 f7           brne    .-10            ; 0x21a <__fixunssfsi+0x42>
 224:   3e f4           brtc    .+14            ; 0x234 <__fixunssfsi+0x5c>
 226:   90 95           com     r25
 228:   80 95           com     r24
 22a:   70 95           com     r23
 22c:   61 95           neg     r22
 22e:   7f 4f           sbci    r23, 0xFF       ; 255
 230:   8f 4f           sbci    r24, 0xFF       ; 255
 232:   9f 4f           sbci    r25, 0xFF       ; 255
 234:   08 95           ret

00000236 <__fp_cmp>:
 236:   99 0f           add     r25, r25
 238:   00 08           sbc     r0, r0
 23a:   55 0f           add     r21, r21
 23c:   aa 0b           sbc     r26, r26
 23e:   e0 e8           ldi     r30, 0x80       ; 128
 240:   fe ef           ldi     r31, 0xFE       ; 254
 242:   16 16           cp      r1, r22
 244:   17 06           cpc     r1, r23
 246:   e8 07           cpc     r30, r24
 248:   f9 07           cpc     r31, r25
 24a:   c0 f0           brcs    .+48            ; 0x27c <__fp_cmp+0x46>
 24c:   12 16           cp      r1, r18
 24e:   13 06           cpc     r1, r19
 250:   e4 07           cpc     r30, r20
 252:   f5 07           cpc     r31, r21
 254:   98 f0           brcs    .+38            ; 0x27c <__fp_cmp+0x46>
 256:   62 1b           sub     r22, r18
 258:   73 0b           sbc     r23, r19
 25a:   84 0b           sbc     r24, r20
 25c:   95 0b           sbc     r25, r21
 25e:   39 f4           brne    .+14            ; 0x26e <__fp_cmp+0x38>
 260:   0a 26           eor     r0, r26
 262:   61 f0           breq    .+24            ; 0x27c <__fp_cmp+0x46>
 264:   23 2b           or      r18, r19
 266:   24 2b           or      r18, r20
 268:   25 2b           or      r18, r21
 26a:   21 f4           brne    .+8             ; 0x274 <__fp_cmp+0x3e>
 26c:   08 95           ret
 26e:   0a 26           eor     r0, r26
 270:   09 f4           brne    .+2             ; 0x274 <__fp_cmp+0x3e>
 272:   a1 40           sbci    r26, 0x01       ; 1
 274:   a6 95           lsr     r26
 276:   8f ef           ldi     r24, 0xFF       ; 255
 278:   81 1d           adc     r24, r1
 27a:   81 1d           adc     r24, r1
 27c:   08 95           ret

0000027e <__fp_split3>:
 27e:   57 fd           sbrc    r21, 7
 280:   90 58           subi    r25, 0x80       ; 128
 282:   44 0f           add     r20, r20
 284:   55 1f           adc     r21, r21
 286:   59 f0           breq    .+22            ; 0x29e <__fp_splitA+0x10>
 288:   5f 3f           cpi     r21, 0xFF       ; 255
 28a:   71 f0           breq    .+28            ; 0x2a8 <__fp_splitA+0x1a>
 28c:   47 95           ror     r20

0000028e <__fp_splitA>:
 28e:   88 0f           add     r24, r24
 290:   97 fb           bst     r25, 7
 292:   99 1f           adc     r25, r25
 294:   61 f0           breq    .+24            ; 0x2ae <__fp_splitA+0x20>
 296:   9f 3f           cpi     r25, 0xFF       ; 255
 298:   79 f0           breq    .+30            ; 0x2b8 <__fp_splitA+0x2a>
 29a:   87 95           ror     r24
 29c:   08 95           ret
 29e:   12 16           cp      r1, r18
 2a0:   13 06           cpc     r1, r19
 2a2:   14 06           cpc     r1, r20
 2a4:   55 1f           adc     r21, r21
 2a6:   f2 cf           rjmp    .-28            ; 0x28c <__fp_split3+0xe>
 2a8:   46 95           lsr     r20
 2aa:   f1 df           rcall   .-30            ; 0x28e <__fp_splitA>
 2ac:   08 c0           rjmp    .+16            ; 0x2be <__fp_splitA+0x30>
 2ae:   16 16           cp      r1, r22
 2b0:   17 06           cpc     r1, r23
 2b2:   18 06           cpc     r1, r24
 2b4:   99 1f           adc     r25, r25
 2b6:   f1 cf           rjmp    .-30            ; 0x29a <__fp_splitA+0xc>
 2b8:   86 95           lsr     r24
 2ba:   71 05           cpc     r23, r1
 2bc:   61 05           cpc     r22, r1
 2be:   08 94           sec
 2c0:   08 95           ret

000002c2 <__fp_zero>:
 2c2:   e8 94           clt

000002c4 <__fp_szero>:
 2c4:   bb 27           eor     r27, r27
 2c6:   66 27           eor     r22, r22
 2c8:   77 27           eor     r23, r23
 2ca:   cb 01           movw    r24, r22
 2cc:   97 f9           bld     r25, 7
 2ce:   08 95           ret

000002d0 <__gesf2>:
 2d0:   0e 94 1b 01     call    0x236   ; 0x236 <__fp_cmp>
 2d4:   08 f4           brcc    .+2             ; 0x2d8 <__gesf2+0x8>
 2d6:   8f ef           ldi     r24, 0xFF       ; 255
 2d8:   08 95           ret

000002da <__mulsf3>:
 2da:   0e 94 80 01     call    0x300   ; 0x300 <__mulsf3x>
 2de:   0c 94 f1 01     jmp     0x3e2   ; 0x3e2 <__fp_round>
 2e2:   0e 94 e3 01     call    0x3c6   ; 0x3c6 <__fp_pscA>
 2e6:   38 f0           brcs    .+14            ; 0x2f6 <__mulsf3+0x1c>
 2e8:   0e 94 ea 01     call    0x3d4   ; 0x3d4 <__fp_pscB>
 2ec:   20 f0           brcs    .+8             ; 0x2f6 <__mulsf3+0x1c>
 2ee:   95 23           and     r25, r21
 2f0:   11 f0           breq    .+4             ; 0x2f6 <__mulsf3+0x1c>
 2f2:   0c 94 da 01     jmp     0x3b4   ; 0x3b4 <__fp_inf>
 2f6:   0c 94 e0 01     jmp     0x3c0   ; 0x3c0 <__fp_nan>
 2fa:   11 24           eor     r1, r1
 2fc:   0c 94 62 01     jmp     0x2c4   ; 0x2c4 <__fp_szero>

00000300 <__mulsf3x>:
 300:   0e 94 3f 01     call    0x27e   ; 0x27e <__fp_split3>
 304:   70 f3           brcs    .-36            ; 0x2e2 <__mulsf3+0x8>

00000306 <__mulsf3_pse>:
 306:   95 9f           mul     r25, r21
 308:   c1 f3           breq    .-16            ; 0x2fa <__mulsf3+0x20>
 30a:   95 0f           add     r25, r21
 30c:   50 e0           ldi     r21, 0x00       ; 0
 30e:   55 1f           adc     r21, r21
 310:   62 9f           mul     r22, r18
 312:   f0 01           movw    r30, r0
 314:   72 9f           mul     r23, r18
 316:   bb 27           eor     r27, r27
 318:   f0 0d           add     r31, r0
 31a:   b1 1d           adc     r27, r1
 31c:   63 9f           mul     r22, r19
 31e:   aa 27           eor     r26, r26
 320:   f0 0d           add     r31, r0
 322:   b1 1d           adc     r27, r1
 324:   aa 1f           adc     r26, r26
 326:   64 9f           mul     r22, r20
 328:   66 27           eor     r22, r22
 32a:   b0 0d           add     r27, r0
 32c:   a1 1d           adc     r26, r1
 32e:   66 1f           adc     r22, r22
 330:   82 9f           mul     r24, r18
 332:   22 27           eor     r18, r18
 334:   b0 0d           add     r27, r0
 336:   a1 1d           adc     r26, r1
 338:   62 1f           adc     r22, r18
 33a:   73 9f           mul     r23, r19
 33c:   b0 0d           add     r27, r0
 33e:   a1 1d           adc     r26, r1
 340:   62 1f           adc     r22, r18
 342:   83 9f           mul     r24, r19
 344:   a0 0d           add     r26, r0
 346:   61 1d           adc     r22, r1
 348:   22 1f           adc     r18, r18
 34a:   74 9f           mul     r23, r20
 34c:   33 27           eor     r19, r19
 34e:   a0 0d           add     r26, r0
 350:   61 1d           adc     r22, r1
 352:   23 1f           adc     r18, r19
 354:   84 9f           mul     r24, r20
 356:   60 0d           add     r22, r0
 358:   21 1d           adc     r18, r1
 35a:   82 2f           mov     r24, r18
 35c:   76 2f           mov     r23, r22
 35e:   6a 2f           mov     r22, r26
 360:   11 24           eor     r1, r1
 362:   9f 57           subi    r25, 0x7F       ; 127
 364:   50 40           sbci    r21, 0x00       ; 0
 366:   9a f0           brmi    .+38            ; 0x38e <__mulsf3_pse+0x88>
 368:   f1 f0           breq    .+60            ; 0x3a6 <__mulsf3_pse+0xa0>
 36a:   88 23           and     r24, r24
 36c:   4a f0           brmi    .+18            ; 0x380 <__mulsf3_pse+0x7a>
 36e:   ee 0f           add     r30, r30
 370:   ff 1f           adc     r31, r31
 372:   bb 1f           adc     r27, r27
 374:   66 1f           adc     r22, r22
 376:   77 1f           adc     r23, r23
 378:   88 1f           adc     r24, r24
 37a:   91 50           subi    r25, 0x01       ; 1
 37c:   50 40           sbci    r21, 0x00       ; 0
 37e:   a9 f7           brne    .-22            ; 0x36a <__mulsf3_pse+0x64>
 380:   9e 3f           cpi     r25, 0xFE       ; 254
 382:   51 05           cpc     r21, r1
 384:   80 f0           brcs    .+32            ; 0x3a6 <__mulsf3_pse+0xa0>
 386:   0c 94 da 01     jmp     0x3b4   ; 0x3b4 <__fp_inf>
 38a:   0c 94 62 01     jmp     0x2c4   ; 0x2c4 <__fp_szero>
 38e:   5f 3f           cpi     r21, 0xFF       ; 255
 390:   e4 f3           brlt    .-8             ; 0x38a <__mulsf3_pse+0x84>
 392:   98 3e           cpi     r25, 0xE8       ; 232
 394:   d4 f3           brlt    .-12            ; 0x38a <__mulsf3_pse+0x84>
 396:   86 95           lsr     r24
 398:   77 95           ror     r23
 39a:   67 95           ror     r22
 39c:   b7 95           ror     r27
 39e:   f7 95           ror     r31
 3a0:   e7 95           ror     r30
 3a2:   9f 5f           subi    r25, 0xFF       ; 255
 3a4:   c1 f7           brne    .-16            ; 0x396 <__mulsf3_pse+0x90>
 3a6:   fe 2b           or      r31, r30
 3a8:   88 0f           add     r24, r24
 3aa:   91 1d           adc     r25, r1
 3ac:   96 95           lsr     r25
 3ae:   87 95           ror     r24
 3b0:   97 f9           bld     r25, 7
 3b2:   08 95           ret

000003b4 <__fp_inf>:
 3b4:   97 f9           bld     r25, 7
 3b6:   9f 67           ori     r25, 0x7F       ; 127
 3b8:   80 e8           ldi     r24, 0x80       ; 128
 3ba:   70 e0           ldi     r23, 0x00       ; 0
 3bc:   60 e0           ldi     r22, 0x00       ; 0
 3be:   08 95           ret

000003c0 <__fp_nan>:
 3c0:   9f ef           ldi     r25, 0xFF       ; 255
 3c2:   80 ec           ldi     r24, 0xC0       ; 192
 3c4:   08 95           ret

000003c6 <__fp_pscA>:
 3c6:   00 24           eor     r0, r0
 3c8:   0a 94           dec     r0
 3ca:   16 16           cp      r1, r22
 3cc:   17 06           cpc     r1, r23
 3ce:   18 06           cpc     r1, r24
 3d0:   09 06           cpc     r0, r25
 3d2:   08 95           ret

000003d4 <__fp_pscB>:
 3d4:   00 24           eor     r0, r0
 3d6:   0a 94           dec     r0
 3d8:   12 16           cp      r1, r18
 3da:   13 06           cpc     r1, r19
 3dc:   14 06           cpc     r1, r20
 3de:   05 06           cpc     r0, r21
 3e0:   08 95           ret

000003e2 <__fp_round>:
 3e2:   09 2e           mov     r0, r25
 3e4:   03 94           inc     r0
 3e6:   00 0c           add     r0, r0
 3e8:   11 f4           brne    .+4             ; 0x3ee <__fp_round+0xc>
 3ea:   88 23           and     r24, r24
 3ec:   52 f0           brmi    .+20            ; 0x402 <__LOCK_REGION_LENGTH__+0x2>
 3ee:   bb 0f           add     r27, r27
 3f0:   40 f4           brcc    .+16            ; 0x402 <__LOCK_REGION_LENGTH__+0x2>
 3f2:   bf 2b           or      r27, r31
 3f4:   11 f4           brne    .+4             ; 0x3fa <__fp_round+0x18>
 3f6:   60 ff           sbrs    r22, 0
 3f8:   04 c0           rjmp    .+8             ; 0x402 <__LOCK_REGION_LENGTH__+0x2>
 3fa:   6f 5f           subi    r22, 0xFF       ; 255
 3fc:   7f 4f           sbci    r23, 0xFF       ; 255
 3fe:   8f 4f           sbci    r24, 0xFF       ; 255
 400:   9f 4f           sbci    r25, 0xFF       ; 255
 402:   08 95           ret

00000404 <_exit>:
 404:   f8 94           cli

00000406 <__stop_program>:
 406:   ff cf           rjmp    .-2             ; 0x406 <__stop_program>

D:\atmel_avr\avr8-gnu-toolchain-win32_x86\bin>avr-gcc -mmcu=atmega328p -Os -g avr.c -o avr.elf

D:\atmel_avr\avr8-gnu-toolchain-win32_x86\bin>avr-objdump -S avr.elf

avr.elf:     file format elf32-avr

Disassembly of section .text:

00000000 <__vectors>:
   0:   0c 94 34 00     jmp     0x68    ; 0x68 <__ctors_end>
   4:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
   8:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
   c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  10:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  14:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  18:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  1c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  20:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  24:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  28:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  2c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  30:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  34:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  38:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  3c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  40:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  44:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  48:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  4c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  50:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  54:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  58:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  5c:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  60:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>
  64:   0c 94 3e 00     jmp     0x7c    ; 0x7c <__bad_interrupt>

00000068 <__ctors_end>:
  68:   11 24           eor     r1, r1
  6a:   1f be           out     0x3f, r1        ; 63
  6c:   cf ef           ldi     r28, 0xFF       ; 255
  6e:   d8 e0           ldi     r29, 0x08       ; 8
  70:   de bf           out     0x3e, r29       ; 62
  72:   cd bf           out     0x3d, r28       ; 61
  74:   0e 94 40 00     call    0x80    ; 0x80 <main>
  78:   0c 94 54 00     jmp     0xa8    ; 0xa8 <_exit>

0000007c <__bad_interrupt>:
  7c:   0c 94 00 00     jmp     0       ; 0x0 <__vectors>

00000080 <main>:
#define F_CPU 1000000UL
#include <avr/io.h>
#include <util/delay.h>

int main(void) {
    DDRB = 0xFF;
  80:   8f ef           ldi     r24, 0xFF       ; 255
  82:   84 b9           out     0x04, r24       ; 4
    DDRC = 0xFF;
  84:   87 b9           out     0x07, r24       ; 7
    DDRD = 0xFF;
  86:   8a b9           out     0x0a, r24       ; 10
    while(1) {
        PORTB ^= 0xFF;
  88:   85 b1           in      r24, 0x05       ; 5
  8a:   80 95           com     r24
  8c:   85 b9           out     0x05, r24       ; 5
        PORTC ^= 0xFF;
  8e:   88 b1           in      r24, 0x08       ; 8
  90:   80 95           com     r24
  92:   88 b9           out     0x08, r24       ; 8
        PORTD ^= 0xFF;
  94:   8b b1           in      r24, 0x0b       ; 11
  96:   80 95           com     r24
  98:   8b b9           out     0x0b, r24       ; 11
        #else
                //round up by default
                __ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
        #endif

        __builtin_avr_delay_cycles(__ticks_dc);
  9a:   87 ea           ldi     r24, 0xA7       ; 167
  9c:   91 e6           ldi     r25, 0x61       ; 97
  9e:   01 97           sbiw    r24, 0x01       ; 1
  a0:   f1 f7           brne    .-4             ; 0x9e <main+0x1e>
  a2:   00 c0           rjmp    .+0             ; 0xa4 <main+0x24>
  a4:   00 00           nop
  a6:   f0 cf           rjmp    .-32            ; 0x88 <main+0x8>

000000a8 <_exit>:
  a8:   f8 94           cli

000000aa <__stop_program>:
  aa:   ff cf           rjmp    .-2             ; 0xaa <__stop_program>

The red generated code is the version with optimisation disabled, the blue is with it enabled. Perhaps it was unfair to include the _delay_ms() which goes potty if optimisation is not enabled? Even without that the difference is:

00000080 <main>:
#include <avr/io.h>

int main(void) {
  80:   cf 93           push    r28
  82:   df 93           push    r29
  84:   cd b7           in      r28, 0x3d       ; 61
  86:   de b7           in      r29, 0x3e       ; 62
    DDRB = 0xFF;
  88:   84 e2           ldi     r24, 0x24       ; 36
  8a:   90 e0           ldi     r25, 0x00       ; 0
  8c:   2f ef           ldi     r18, 0xFF       ; 255
  8e:   fc 01           movw    r30, r24
  90:   20 83           st      Z, r18
    DDRC = 0xFF;
  92:   87 e2           ldi     r24, 0x27       ; 39
  94:   90 e0           ldi     r25, 0x00       ; 0
  96:   2f ef           ldi     r18, 0xFF       ; 255
  98:   fc 01           movw    r30, r24
  9a:   20 83           st      Z, r18
    DDRD = 0xFF;
  9c:   8a e2           ldi     r24, 0x2A       ; 42
  9e:   90 e0           ldi     r25, 0x00       ; 0
  a0:   2f ef           ldi     r18, 0xFF       ; 255
  a2:   fc 01           movw    r30, r24
  a4:   20 83           st      Z, r18
    while(1) {
        PORTB ^= 0xFF;
  a6:   85 e2           ldi     r24, 0x25       ; 37
  a8:   90 e0           ldi     r25, 0x00       ; 0
  aa:   25 e2           ldi     r18, 0x25       ; 37
  ac:   30 e0           ldi     r19, 0x00       ; 0
  ae:   f9 01           movw    r30, r18
  b0:   20 81           ld      r18, Z
  b2:   20 95           com     r18
  b4:   fc 01           movw    r30, r24
  b6:   20 83           st      Z, r18
        PORTC ^= 0xFF;
  b8:   88 e2           ldi     r24, 0x28       ; 40
  ba:   90 e0           ldi     r25, 0x00       ; 0
  bc:   28 e2           ldi     r18, 0x28       ; 40
  be:   30 e0           ldi     r19, 0x00       ; 0
  c0:   f9 01           movw    r30, r18
  c2:   20 81           ld      r18, Z
  c4:   20 95           com     r18
  c6:   fc 01           movw    r30, r24
  c8:   20 83           st      Z, r18
        PORTD ^= 0xFF;
  ca:   8b e2           ldi     r24, 0x2B       ; 43
  cc:   90 e0           ldi     r25, 0x00       ; 0
  ce:   2b e2           ldi     r18, 0x2B       ; 43
  d0:   30 e0           ldi     r19, 0x00       ; 0
  d2:   f9 01           movw    r30, r18
  d4:   20 81           ld      r18, Z
  d6:   20 95           com     r18
  d8:   fc 01           movw    r30, r24
  da:   20 83           st      Z, r18
    }
  dc:   e4 cf           rjmp    .-56            ; 0xa6 <main+0x26>
00000080 <main>:
#include <avr/io.h>

int main(void) {
    DDRB = 0xFF;
  80:   8f ef           ldi     r24, 0xFF       ; 255
  82:   84 b9           out     0x04, r24       ; 4
    DDRC = 0xFF;
  84:   87 b9           out     0x07, r24       ; 7
    DDRD = 0xFF;
  86:   8a b9           out     0x0a, r24       ; 10
    while(1) {
        PORTB ^= 0xFF;
  88:   85 b1           in      r24, 0x05       ; 5
  8a:   80 95           com     r24
  8c:   85 b9           out     0x05, r24       ; 5
        PORTC ^= 0xFF;
  8e:   88 b1           in      r24, 0x08       ; 8
  90:   80 95           com     r24
  92:   88 b9           out     0x08, r24       ; 8
        PORTD ^= 0xFF;
  94:   8b b1           in      r24, 0x0b       ; 11
  96:   80 95           com     r24
  98:   8b b9           out     0x0b, r24       ; 11
  9a:   f6 cf           rjmp    .-20            ; 0x88 <main+0x8>

That is more than just 5..10% !!

Last Edited: Wed. Aug 15, 2018 - 08:39 AM
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clawson wrote:

Brian Fairchild wrote:
You buy a new car and you don't waste time wishing it did 130MPH instead of 120MPH do you?
Err, speak for yourself! (top speed may not matter per se but it's a likely indication of aerodynamics and engine power which DO matter!)

 

Depends, many EVs are electronically limited but still have masses of power right up to maximum speed. My old Leaf was like that, loads of power even at motorway speeds but electronically limited to ~100 MPH. Actually it could do 96 MPH in reverse too.

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Total votes: 1

then people will move on to something else.

I did https://www.avrfreaks.net/forum/... as long as they keep the Xmeag32E5 going for a few more years I'm happy.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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@clawson

 

As much as I brutally hate XC8 with a passion and MPLAB X which are both third-world quality compared to tools actually meant for C (VS, CLion, etc).....

 

AVR-GCC in this situation hasn't been gimped. I opened up Studio 7. Selected the ATMega328P and compiled the same code and got the same raw list file.

 

What you are "doing wrong" is not using -O1 which is the studio default. XC8 isn't charging for -O1 either.

 

 

GccApplication2.elf:     file format elf32-avr

 

Sections:

Idx Name          Size      VMA       LMA       File off  Algn

  0 .data         00000000  00800100  00800100  0000045c  2**0

                  CONTENTS, ALLOC, LOAD, DATA

  1 .text         00000408  00000000  00000000  00000054  2**1

                  CONTENTS, ALLOC, LOAD, READONLY, CODE

  2 .comment      00000030  00000000  00000000  0000045c  2**0

                  CONTENTS, READONLY

  3 .note.gnu.avr.deviceinfo 00000040  00000000  00000000  0000048c  2**2

                  CONTENTS, READONLY

  4 .debug_aranges 00000020  00000000  00000000  000004cc  2**0

                  CONTENTS, READONLY, DEBUGGING

  5 .debug_info   0000073c  00000000  00000000  000004ec  2**0

                  CONTENTS, READONLY, DEBUGGING

  6 .debug_abbrev 0000065b  00000000  00000000  00000c28  2**0

                  CONTENTS, READONLY, DEBUGGING

  7 .debug_line   000002d2  00000000  00000000  00001283  2**0

                  CONTENTS, READONLY, DEBUGGING

  8 .debug_frame  00000034  00000000  00000000  00001558  2**2

                  CONTENTS, READONLY, DEBUGGING

  9 .debug_str    00000384  00000000  00000000  0000158c  2**0

                  CONTENTS, READONLY, DEBUGGING

 10 .debug_loc    00000047  00000000  00000000  00001910  2**0

                  CONTENTS, READONLY, DEBUGGING

 11 .debug_ranges 00000010  00000000  00000000  00001957  2**0

                  CONTENTS, READONLY, DEBUGGING

 

Disassembly of section .text:

 

00000000 <__vectors>:

   0: 0c 94 34 00 jmp 0x68 ; 0x68 <__ctors_end>

   4: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

   8: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

   c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  10: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  14: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  18: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  1c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  20: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  24: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  28: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  2c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  30: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  34: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  38: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  3c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  40: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  44: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  48: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  4c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  50: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  54: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  58: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  5c: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  60: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

  64: 0c 94 3e 00 jmp 0x7c ; 0x7c <__bad_interrupt>

 

00000068 <__ctors_end>:

  68: 11 24        eor r1, r1

  6a: 1f be        out 0x3f, r1 ; 63

  6c: cf ef        ldi r28, 0xFF ; 255

  6e: d8 e0        ldi r29, 0x08 ; 8

  70: de bf        out 0x3e, r29 ; 62

  72: cd bf        out 0x3d, r28 ; 61

  74: 0e 94 40 00 call 0x80 ; 0x80 <main>

  78: 0c 94 02 02 jmp 0x404 ; 0x404 <_exit>

 

0000007c <__bad_interrupt>:

  7c: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>

 

00000080 <main>:

 */ 

#define F_CPU 1000000UL

#include <avr/io.h>

#include <util/delay.h>

 

int main(void) {

  80: cf 93        push r28

  82: df 93        push r29

  84: cd b7        in r28, 0x3d ; 61

  86: de b7        in r29, 0x3e ; 62

  88: 2e 97        sbiw r28, 0x0e ; 14

  8a: 0f b6        in r0, 0x3f ; 63

  8c: f8 94        cli

  8e: de bf        out 0x3e, r29 ; 62

  90: 0f be        out 0x3f, r0 ; 63

  92: cd bf        out 0x3d, r28 ; 61

DDRB = 0xFF;

  94: 84 e2        ldi r24, 0x24 ; 36

  96: 90 e0        ldi r25, 0x00 ; 0

  98: 2f ef        ldi r18, 0xFF ; 255

  9a: fc 01        movw r30, r24

  9c: 20 83        st Z, r18

DDRC = 0xFF;

  9e: 87 e2        ldi r24, 0x27 ; 39

  a0: 90 e0        ldi r25, 0x00 ; 0

  a2: 2f ef        ldi r18, 0xFF ; 255

  a4: fc 01        movw r30, r24

  a6: 20 83        st Z, r18

DDRD = 0xFF;

  a8: 8a e2        ldi r24, 0x2A ; 42

  aa: 90 e0        ldi r25, 0x00 ; 0

  ac: 2f ef        ldi r18, 0xFF ; 255

  ae: fc 01        movw r30, r24

  b0: 20 83        st Z, r18

while(1) {

PORTB ^= 0xFF;

  b2: 85 e2        ldi r24, 0x25 ; 37

  b4: 90 e0        ldi r25, 0x00 ; 0

  b6: 25 e2        ldi r18, 0x25 ; 37

  b8: 30 e0        ldi r19, 0x00 ; 0

  ba: f9 01        movw r30, r18

  bc: 20 81        ld r18, Z

  be: 20 95        com r18

  c0: fc 01        movw r30, r24

  c2: 20 83        st Z, r18

PORTC ^= 0xFF;

  c4: 88 e2        ldi r24, 0x28 ; 40

  c6: 90 e0        ldi r25, 0x00 ; 0

  c8: 28 e2        ldi r18, 0x28 ; 40

  ca: 30 e0        ldi r19, 0x00 ; 0

  cc: f9 01        movw r30, r18

  ce: 20 81        ld r18, Z

  d0: 20 95        com r18

  d2: fc 01        movw r30, r24

  d4: 20 83        st Z, r18

PORTD ^= 0xFF;

  d6: 8b e2        ldi r24, 0x2B ; 43

  d8: 90 e0        ldi r25, 0x00 ; 0

  da: 2b e2        ldi r18, 0x2B ; 43

  dc: 30 e0        ldi r19, 0x00 ; 0

  de: f9 01        movw r30, r18

  e0: 20 81        ld r18, Z

  e2: 20 95        com r18

  e4: fc 01        movw r30, r24

  e6: 20 83        st Z, r18

  e8: 80 e0        ldi r24, 0x00 ; 0

  ea: 90 e0        ldi r25, 0x00 ; 0

  ec: a8 ec        ldi r26, 0xC8 ; 200

  ee: b2 e4        ldi r27, 0x42 ; 66

  f0: 89 83        std Y+1, r24 ; 0x01

  f2: 9a 83        std Y+2, r25 ; 0x02

  f4: ab 83        std Y+3, r26 ; 0x03

  f6: bc 83        std Y+4, r27 ; 0x04

 

__builtin_avr_delay_cycles(__ticks_dc);

 

#else

uint16_t __ticks;

__tmp = ((F_CPU) / 4e3) * __ms;

  f8: 20 e0        ldi r18, 0x00 ; 0

  fa: 30 e0        ldi r19, 0x00 ; 0

  fc: 4a e7        ldi r20, 0x7A ; 122

  fe: 53 e4        ldi r21, 0x43 ; 67

 100: 69 81        ldd r22, Y+1 ; 0x01

 102: 7a 81        ldd r23, Y+2 ; 0x02

 104: 8b 81        ldd r24, Y+3 ; 0x03

 106: 9c 81        ldd r25, Y+4 ; 0x04

 108: 0e 94 6d 01 call 0x2da ; 0x2da <__mulsf3>

 10c: dc 01        movw r26, r24

 10e: cb 01        movw r24, r22

 110: 8d 83        std Y+5, r24 ; 0x05

 112: 9e 83        std Y+6, r25 ; 0x06

 114: af 83        std Y+7, r26 ; 0x07

 116: b8 87        std Y+8, r27 ; 0x08

if (__tmp < 1.0)

 118: 20 e0        ldi r18, 0x00 ; 0

 11a: 30 e0        ldi r19, 0x00 ; 0

 11c: 40 e8        ldi r20, 0x80 ; 128

 11e: 5f e3        ldi r21, 0x3F ; 63

 120: 6d 81        ldd r22, Y+5 ; 0x05

 122: 7e 81        ldd r23, Y+6 ; 0x06

 124: 8f 81        ldd r24, Y+7 ; 0x07

 126: 98 85        ldd r25, Y+8 ; 0x08

 128: 0e 94 e7 00 call 0x1ce ; 0x1ce <__cmpsf2>

 12c: 88 23        and r24, r24

 12e: 2c f4        brge .+10      ; 0x13a <main+0xba>

__ticks = 1;

 130: 81 e0        ldi r24, 0x01 ; 1

 132: 90 e0        ldi r25, 0x00 ; 0

 134: 9a 87        std Y+10, r25 ; 0x0a

 136: 89 87        std Y+9, r24 ; 0x09

 138: 3f c0        rjmp .+126    ; 0x1b8 <main+0x138>

else if (__tmp > 65535)

 13a: 20 e0        ldi r18, 0x00 ; 0

 13c: 3f ef        ldi r19, 0xFF ; 255

 13e: 4f e7        ldi r20, 0x7F ; 127

 140: 57 e4        ldi r21, 0x47 ; 71

 142: 6d 81        ldd r22, Y+5 ; 0x05

 144: 7e 81        ldd r23, Y+6 ; 0x06

 146: 8f 81        ldd r24, Y+7 ; 0x07

 148: 98 85        ldd r25, Y+8 ; 0x08

 14a: 0e 94 68 01 call 0x2d0 ; 0x2d0 <__gesf2>

 14e: 18 16        cp r1, r24

 150: 4c f5        brge .+82      ; 0x1a4 <main+0x124>

{

// __ticks = requested delay in 1/10 ms

__ticks = (uint16_t) (__ms * 10.0);

 152: 20 e0        ldi r18, 0x00 ; 0

 154: 30 e0        ldi r19, 0x00 ; 0

 156: 40 e2        ldi r20, 0x20 ; 32

 158: 51 e4        ldi r21, 0x41 ; 65

 15a: 69 81        ldd r22, Y+1 ; 0x01

 15c: 7a 81        ldd r23, Y+2 ; 0x02

 15e: 8b 81        ldd r24, Y+3 ; 0x03

 160: 9c 81        ldd r25, Y+4 ; 0x04

 162: 0e 94 6d 01 call 0x2da ; 0x2da <__mulsf3>

 166: dc 01        movw r26, r24

 168: cb 01        movw r24, r22

 16a: bc 01        movw r22, r24

 16c: cd 01        movw r24, r26

 16e: 0e 94 ec 00 call 0x1d8 ; 0x1d8 <__fixunssfsi>

 172: dc 01        movw r26, r24

 174: cb 01        movw r24, r22

 176: 9a 87        std Y+10, r25 ; 0x0a

 178: 89 87        std Y+9, r24 ; 0x09

 17a: 0f c0        rjmp .+30      ; 0x19a <main+0x11a>

 17c: 89 e1        ldi r24, 0x19 ; 25

 17e: 90 e0        ldi r25, 0x00 ; 0

 180: 9c 87        std Y+12, r25 ; 0x0c

 182: 8b 87        std Y+11, r24 ; 0x0b

    milliseconds can be achieved.

 */

void

_delay_loop_2(uint16_t __count)

{

__asm__ volatile (

 184: 8b 85        ldd r24, Y+11 ; 0x0b

 186: 9c 85        ldd r25, Y+12 ; 0x0c

 188: 01 97        sbiw r24, 0x01 ; 1

 18a: f1 f7        brne .-4      ; 0x188 <main+0x108>

 18c: 9c 87        std Y+12, r25 ; 0x0c

 18e: 8b 87        std Y+11, r24 ; 0x0b

while(__ticks)

{

// wait 1/10 ms

_delay_loop_2(((F_CPU) / 4e3) / 10);

__ticks --;

 190: 89 85        ldd r24, Y+9 ; 0x09

 192: 9a 85        ldd r25, Y+10 ; 0x0a

 194: 01 97        sbiw r24, 0x01 ; 1

 196: 9a 87        std Y+10, r25 ; 0x0a

 198: 89 87        std Y+9, r24 ; 0x09

__ticks = 1;

else if (__tmp > 65535)

{

// __ticks = requested delay in 1/10 ms

__ticks = (uint16_t) (__ms * 10.0);

while(__ticks)

 19a: 89 85        ldd r24, Y+9 ; 0x09

 19c: 9a 85        ldd r25, Y+10 ; 0x0a

 19e: 89 2b        or r24, r25

 1a0: 69 f7        brne .-38      ; 0x17c <main+0xfc>

 1a2: 14 c0        rjmp .+40      ; 0x1cc <main+0x14c>

__ticks --;

}

return;

}

else

__ticks = (uint16_t)__tmp;

 1a4: 6d 81        ldd r22, Y+5 ; 0x05

 1a6: 7e 81        ldd r23, Y+6 ; 0x06

 1a8: 8f 81        ldd r24, Y+7 ; 0x07

 1aa: 98 85        ldd r25, Y+8 ; 0x08

 1ac: 0e 94 ec 00 call 0x1d8 ; 0x1d8 <__fixunssfsi>

 1b0: dc 01        movw r26, r24

 1b2: cb 01        movw r24, r22

 1b4: 9a 87        std Y+10, r25 ; 0x0a

 1b6: 89 87        std Y+9, r24 ; 0x09

 1b8: 89 85        ldd r24, Y+9 ; 0x09

 1ba: 9a 85        ldd r25, Y+10 ; 0x0a

 1bc: 9e 87        std Y+14, r25 ; 0x0e

 1be: 8d 87        std Y+13, r24 ; 0x0d

 1c0: 8d 85        ldd r24, Y+13 ; 0x0d

 1c2: 9e 85        ldd r25, Y+14 ; 0x0e

 1c4: 01 97        sbiw r24, 0x01 ; 1

 1c6: f1 f7        brne .-4      ; 0x1c4 <main+0x144>

 1c8: 9e 87        std Y+14, r25 ; 0x0e

 1ca: 8d 87        std Y+13, r24 ; 0x0d

_delay_ms(100);

}

 1cc: 72 cf        rjmp .-284    ; 0xb2 <main+0x32>

 

000001ce <__cmpsf2>:

 1ce: 0e 94 1b 01 call 0x236 ; 0x236 <__fp_cmp>

 1d2: 08 f4        brcc .+2      ; 0x1d6 <__cmpsf2+0x8>

 1d4: 81 e0        ldi r24, 0x01 ; 1

 1d6: 08 95        ret

 

000001d8 <__fixunssfsi>:

 1d8: 0e 94 47 01 call 0x28e ; 0x28e <__fp_splitA>

 1dc: 88 f0        brcs .+34      ; 0x200 <__fixunssfsi+0x28>

 1de: 9f 57        subi r25, 0x7F ; 127

 1e0: 98 f0        brcs .+38      ; 0x208 <__fixunssfsi+0x30>

 1e2: b9 2f        mov r27, r25

 1e4: 99 27        eor r25, r25

 1e6: b7 51        subi r27, 0x17 ; 23

 1e8: b0 f0        brcs .+44      ; 0x216 <__fixunssfsi+0x3e>

 1ea: e1 f0        breq .+56      ; 0x224 <__fixunssfsi+0x4c>

 1ec: 66 0f        add r22, r22

 1ee: 77 1f        adc r23, r23

 1f0: 88 1f        adc r24, r24

 1f2: 99 1f        adc r25, r25

 1f4: 1a f0        brmi .+6      ; 0x1fc <__fixunssfsi+0x24>

 1f6: ba 95        dec r27

 1f8: c9 f7        brne .-14      ; 0x1ec <__fixunssfsi+0x14>

 1fa: 14 c0        rjmp .+40      ; 0x224 <__fixunssfsi+0x4c>

 1fc: b1 30        cpi r27, 0x01 ; 1

 1fe: 91 f0        breq .+36      ; 0x224 <__fixunssfsi+0x4c>

 200: 0e 94 61 01 call 0x2c2 ; 0x2c2 <__fp_zero>

 204: b1 e0        ldi r27, 0x01 ; 1

 206: 08 95        ret

 208: 0c 94 61 01 jmp 0x2c2 ; 0x2c2 <__fp_zero>

 20c: 67 2f        mov r22, r23

 20e: 78 2f        mov r23, r24

 210: 88 27        eor r24, r24

 212: b8 5f        subi r27, 0xF8 ; 248

 214: 39 f0        breq .+14      ; 0x224 <__fixunssfsi+0x4c>

 216: b9 3f        cpi r27, 0xF9 ; 249

 218: cc f3        brlt .-14      ; 0x20c <__fixunssfsi+0x34>

 21a: 86 95        lsr r24

 21c: 77 95        ror r23

 21e: 67 95        ror r22

 220: b3 95        inc r27

 222: d9 f7        brne .-10      ; 0x21a <__fixunssfsi+0x42>

 224: 3e f4        brtc .+14      ; 0x234 <__fixunssfsi+0x5c>

 226: 90 95        com r25

 228: 80 95        com r24

 22a: 70 95        com r23

 22c: 61 95        neg r22

 22e: 7f 4f        sbci r23, 0xFF ; 255

 230: 8f 4f        sbci r24, 0xFF ; 255

 232: 9f 4f        sbci r25, 0xFF ; 255

 234: 08 95        ret

 

00000236 <__fp_cmp>:

 236: 99 0f        add r25, r25

 238: 00 08        sbc r0, r0

 23a: 55 0f        add r21, r21

 23c: aa 0b        sbc r26, r26

 23e: e0 e8        ldi r30, 0x80 ; 128

 240: fe ef        ldi r31, 0xFE ; 254

 242: 16 16        cp r1, r22

 244: 17 06        cpc r1, r23

 246: e8 07        cpc r30, r24

 248: f9 07        cpc r31, r25

 24a: c0 f0        brcs .+48      ; 0x27c <__fp_cmp+0x46>

 24c: 12 16        cp r1, r18

 24e: 13 06        cpc r1, r19

 250: e4 07        cpc r30, r20

 252: f5 07        cpc r31, r21

 254: 98 f0        brcs .+38      ; 0x27c <__fp_cmp+0x46>

 256: 62 1b        sub r22, r18

 258: 73 0b        sbc r23, r19

 25a: 84 0b        sbc r24, r20

 25c: 95 0b        sbc r25, r21

 25e: 39 f4        brne .+14      ; 0x26e <__fp_cmp+0x38>

 260: 0a 26        eor r0, r26

 262: 61 f0        breq .+24      ; 0x27c <__fp_cmp+0x46>

 264: 23 2b        or r18, r19

 266: 24 2b        or r18, r20

 268: 25 2b        or r18, r21

 26a: 21 f4        brne .+8      ; 0x274 <__fp_cmp+0x3e>

 26c: 08 95        ret

 26e: 0a 26        eor r0, r26

 270: 09 f4        brne .+2      ; 0x274 <__fp_cmp+0x3e>

 272: a1 40        sbci r26, 0x01 ; 1

 274: a6 95        lsr r26

 276: 8f ef        ldi r24, 0xFF ; 255

 278: 81 1d        adc r24, r1

 27a: 81 1d        adc r24, r1

 27c: 08 95        ret

 

0000027e <__fp_split3>:

 27e: 57 fd        sbrc r21, 7

 280: 90 58        subi r25, 0x80 ; 128

 282: 44 0f        add r20, r20

 284: 55 1f        adc r21, r21

 286: 59 f0        breq .+22      ; 0x29e <__fp_splitA+0x10>

 288: 5f 3f        cpi r21, 0xFF ; 255

 28a: 71 f0        breq .+28      ; 0x2a8 <__fp_splitA+0x1a>

 28c: 47 95        ror r20

 

0000028e <__fp_splitA>:

 28e: 88 0f        add r24, r24

 290: 97 fb        bst r25, 7

 292: 99 1f        adc r25, r25

 294: 61 f0        breq .+24      ; 0x2ae <__fp_splitA+0x20>

 296: 9f 3f        cpi r25, 0xFF ; 255

 298: 79 f0        breq .+30      ; 0x2b8 <__fp_splitA+0x2a>

 29a: 87 95        ror r24

 29c: 08 95        ret

 29e: 12 16        cp r1, r18

 2a0: 13 06        cpc r1, r19

 2a2: 14 06        cpc r1, r20

 2a4: 55 1f        adc r21, r21

 2a6: f2 cf        rjmp .-28      ; 0x28c <__fp_split3+0xe>

 2a8: 46 95        lsr r20

 2aa: f1 df        rcall .-30      ; 0x28e <__fp_splitA>

 2ac: 08 c0        rjmp .+16      ; 0x2be <__fp_splitA+0x30>

 2ae: 16 16        cp r1, r22

 2b0: 17 06        cpc r1, r23

 2b2: 18 06        cpc r1, r24

 2b4: 99 1f        adc r25, r25

 2b6: f1 cf        rjmp .-30      ; 0x29a <__fp_splitA+0xc>

 2b8: 86 95        lsr r24

 2ba: 71 05        cpc r23, r1

 2bc: 61 05        cpc r22, r1

 2be: 08 94        sec

 2c0: 08 95        ret

 

000002c2 <__fp_zero>:

 2c2: e8 94        clt

 

000002c4 <__fp_szero>:

 2c4: bb 27        eor r27, r27

 2c6: 66 27        eor r22, r22

 2c8: 77 27        eor r23, r23

 2ca: cb 01        movw r24, r22

 2cc: 97 f9        bld r25, 7

 2ce: 08 95        ret

 

000002d0 <__gesf2>:

 2d0: 0e 94 1b 01 call 0x236 ; 0x236 <__fp_cmp>

 2d4: 08 f4        brcc .+2      ; 0x2d8 <__gesf2+0x8>

 2d6: 8f ef        ldi r24, 0xFF ; 255

 2d8: 08 95        ret

 

000002da <__mulsf3>:

 2da: 0e 94 80 01 call 0x300 ; 0x300 <__mulsf3x>

 2de: 0c 94 f1 01 jmp 0x3e2 ; 0x3e2 <__fp_round>

 2e2: 0e 94 e3 01 call 0x3c6 ; 0x3c6 <__fp_pscA>

 2e6: 38 f0        brcs .+14      ; 0x2f6 <__mulsf3+0x1c>

 2e8: 0e 94 ea 01 call 0x3d4 ; 0x3d4 <__fp_pscB>

 2ec: 20 f0        brcs .+8      ; 0x2f6 <__mulsf3+0x1c>

 2ee: 95 23        and r25, r21

 2f0: 11 f0        breq .+4      ; 0x2f6 <__mulsf3+0x1c>

 2f2: 0c 94 da 01 jmp 0x3b4 ; 0x3b4 <__fp_inf>

 2f6: 0c 94 e0 01 jmp 0x3c0 ; 0x3c0 <__fp_nan>

 2fa: 11 24        eor r1, r1

 2fc: 0c 94 62 01 jmp 0x2c4 ; 0x2c4 <__fp_szero>

 

00000300 <__mulsf3x>:

 300: 0e 94 3f 01 call 0x27e ; 0x27e <__fp_split3>

 304: 70 f3        brcs .-36      ; 0x2e2 <__mulsf3+0x8>

 

00000306 <__mulsf3_pse>:

 306: 95 9f        mul r25, r21

 308: c1 f3        breq .-16      ; 0x2fa <__mulsf3+0x20>

 30a: 95 0f        add r25, r21

 30c: 50 e0        ldi r21, 0x00 ; 0

 30e: 55 1f        adc r21, r21

 310: 62 9f        mul r22, r18

 312: f0 01        movw r30, r0

 314: 72 9f        mul r23, r18

 316: bb 27        eor r27, r27

 318: f0 0d        add r31, r0

 31a: b1 1d        adc r27, r1

 31c: 63 9f        mul r22, r19

 31e: aa 27        eor r26, r26

 320: f0 0d        add r31, r0

 322: b1 1d        adc r27, r1

 324: aa 1f        adc r26, r26

 326: 64 9f        mul r22, r20

 328: 66 27        eor r22, r22

 32a: b0 0d        add r27, r0

 32c: a1 1d        adc r26, r1

 32e: 66 1f        adc r22, r22

 330: 82 9f        mul r24, r18

 332: 22 27        eor r18, r18

 334: b0 0d        add r27, r0

 336: a1 1d        adc r26, r1

 338: 62 1f        adc r22, r18

 33a: 73 9f        mul r23, r19

 33c: b0 0d        add r27, r0

 33e: a1 1d        adc r26, r1

 340: 62 1f        adc r22, r18

 342: 83 9f        mul r24, r19

 344: a0 0d        add r26, r0

 346: 61 1d        adc r22, r1

 348: 22 1f        adc r18, r18

 34a: 74 9f        mul r23, r20

 34c: 33 27        eor r19, r19

 34e: a0 0d        add r26, r0

 350: 61 1d        adc r22, r1

 352: 23 1f        adc r18, r19

 354: 84 9f        mul r24, r20

 356: 60 0d        add r22, r0

 358: 21 1d        adc r18, r1

 35a: 82 2f        mov r24, r18

 35c: 76 2f        mov r23, r22

 35e: 6a 2f        mov r22, r26

 360: 11 24        eor r1, r1

 362: 9f 57        subi r25, 0x7F ; 127

 364: 50 40        sbci r21, 0x00 ; 0

 366: 9a f0        brmi .+38      ; 0x38e <__mulsf3_pse+0x88>

 368: f1 f0        breq .+60      ; 0x3a6 <__mulsf3_pse+0xa0>

 36a: 88 23        and r24, r24

 36c: 4a f0        brmi .+18      ; 0x380 <__mulsf3_pse+0x7a>

 36e: ee 0f        add r30, r30

 370: ff 1f        adc r31, r31

 372: bb 1f        adc r27, r27

 374: 66 1f        adc r22, r22

 376: 77 1f        adc r23, r23

 378: 88 1f        adc r24, r24

 37a: 91 50        subi r25, 0x01 ; 1

 37c: 50 40        sbci r21, 0x00 ; 0

 37e: a9 f7        brne .-22      ; 0x36a <__mulsf3_pse+0x64>

 380: 9e 3f        cpi r25, 0xFE ; 254

 382: 51 05        cpc r21, r1

 384: 80 f0        brcs .+32      ; 0x3a6 <__mulsf3_pse+0xa0>

 386: 0c 94 da 01 jmp 0x3b4 ; 0x3b4 <__fp_inf>

 38a: 0c 94 62 01 jmp 0x2c4 ; 0x2c4 <__fp_szero>

 38e: 5f 3f        cpi r21, 0xFF ; 255

 390: e4 f3        brlt .-8      ; 0x38a <__mulsf3_pse+0x84>

 392: 98 3e        cpi r25, 0xE8 ; 232

 394: d4 f3        brlt .-12      ; 0x38a <__mulsf3_pse+0x84>

 396: 86 95        lsr r24

 398: 77 95        ror r23

 39a: 67 95        ror r22

 39c: b7 95        ror r27

 39e: f7 95        ror r31

 3a0: e7 95        ror r30

 3a2: 9f 5f        subi r25, 0xFF ; 255

 3a4: c1 f7        brne .-16      ; 0x396 <__mulsf3_pse+0x90>

 3a6: fe 2b        or r31, r30

 3a8: 88 0f        add r24, r24

 3aa: 91 1d        adc r25, r1

 3ac: 96 95        lsr r25

 3ae: 87 95        ror r24

 3b0: 97 f9        bld r25, 7

 3b2: 08 95        ret

 

000003b4 <__fp_inf>:

 3b4: 97 f9        bld r25, 7

 3b6: 9f 67        ori r25, 0x7F ; 127

 3b8: 80 e8        ldi r24, 0x80 ; 128

 3ba: 70 e0        ldi r23, 0x00 ; 0

 3bc: 60 e0        ldi r22, 0x00 ; 0

 3be: 08 95        ret

 

000003c0 <__fp_nan>:

 3c0: 9f ef        ldi r25, 0xFF ; 255

 3c2: 80 ec        ldi r24, 0xC0 ; 192

 3c4: 08 95        ret

 

000003c6 <__fp_pscA>:

 3c6: 00 24        eor r0, r0

 3c8: 0a 94        dec r0

 3ca: 16 16        cp r1, r22

 3cc: 17 06        cpc r1, r23

 3ce: 18 06        cpc r1, r24

 3d0: 09 06        cpc r0, r25

 3d2: 08 95        ret

 

000003d4 <__fp_pscB>:

 3d4: 00 24        eor r0, r0

 3d6: 0a 94        dec r0

 3d8: 12 16        cp r1, r18

 3da: 13 06        cpc r1, r19

 3dc: 14 06        cpc r1, r20

 3de: 05 06        cpc r0, r21

 3e0: 08 95        ret

 

000003e2 <__fp_round>:

 3e2: 09 2e        mov r0, r25

 3e4: 03 94        inc r0

 3e6: 00 0c        add r0, r0

 3e8: 11 f4        brne .+4      ; 0x3ee <__fp_round+0xc>

 3ea: 88 23        and r24, r24

 3ec: 52 f0        brmi .+20      ; 0x402 <__LOCK_REGION_LENGTH__+0x2>

 3ee: bb 0f        add r27, r27

 3f0: 40 f4        brcc .+16      ; 0x402 <__LOCK_REGION_LENGTH__+0x2>

 3f2: bf 2b        or r27, r31

 3f4: 11 f4        brne .+4      ; 0x3fa <__fp_round+0x18>

 3f6: 60 ff        sbrs r22, 0

 3f8: 04 c0        rjmp .+8      ; 0x402 <__LOCK_REGION_LENGTH__+0x2>

 3fa: 6f 5f        subi r22, 0xFF ; 255

 3fc: 7f 4f        sbci r23, 0xFF ; 255

 3fe: 8f 4f        sbci r24, 0xFF ; 255

 400: 9f 4f        sbci r25, 0xFF ; 255

 402: 08 95        ret

 

00000404 <_exit>:

 404: f8 94        cli

 

00000406 <__stop_program>:

 406: ff cf        rjmp .-2      ; 0x406 <__stop_program>

 

Last Edited: Thu. Aug 16, 2018 - 02:35 PM
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Total votes: 1

mroszko wrote:
What you are "doing wrong" is not using -O1
I fear you have entirely missed my point. I deliberately used (and used color highlighting to make the point) -O0 to show what you can get from a C compiler that is not optimising. I'm not saying this is a "good thing". In fact if you look at my signature then point #4 has been saying this very thing for more than a decade! But what I'm saying is that a compiler that makes no attempt to optimise can be ATROCIOUS in its code generation (gcc is!). The suggestion had been that the difference between optimisation on/off might be a 5..10% issue. My point was that it might be a case of code bloated by a factor of 10 or 20 or worse.!!

 

So no optimisation if not a "minor inconvenience" - it is "totally unusable".

 

I imagine that people who charge money to have optimisation switched on know this cheeky

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Total votes: 1

mojo-chan wrote:
If you go over the Microchip forums you will see a night and day difference. No real community

I think you can see somewhat similar between AVRFreaks and the other so-called "communities" here?

 

As someone said (complained, actually) in another manufacturer's forum: there is a big difference between just opening a forum, and actually building a community.

 

 

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I would not get too stressed over Compiler,  Microchip pricing, ....

 

Just try the MPLABX with whatever Tools suite is default.

 

How good is the debugging experience?

How pleasant is it to use e.g. compared to AS7, Keil, Rowley, ...

 

The current AVR Compiler works pretty well.   I would not worry if this is the "free" version.

If you have to pay for a "better" Compiler it is much like GCC vs IAR.  Or ARM-GCC vs the ARM Compiler.   Performance differences are marginal.

 

If the debugger was size-limited like Keil or otherwise crippled.   that would be fatal.

But hey-ho,   this would not be in Microchip's interest.

 

No,  I am not brave enough to try MPLABX yet.    I will let others be the guinea pigs first.

 

David.

Last Edited: Thu. Aug 16, 2018 - 04:01 PM
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david.prentice wrote:

I would not get too stressed over Compiler

 

In a lot of the work I do the compiler is critical. I have invested a lot of time in understanding and gaining experience with AVR-GCC. It's also key to producing good firmware for some of my hobby stuff, and even then sometimes I have to drop down to assembler to get what I need.

 

So for me dropping AVR-GCC support, or just not updating it, means I will probably not ever switch to MPLAB or use new parts that are currently not supported. In fact, it's time to consider alternatives, maybe ARM since then I'm not tied to one vendor.

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I am quite happy to use ARM-GCC even if the ARM tools are marginally better.
I would guess that the new XTiny chips have a similar compiler-model to Xmega.
So any new chips require no more than header files.
.
There is little point in getting upset. Just wait and see how MPLAB plays out.
Project build is trivial. Debug and Simulation are the critical areas.
.
David.

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