ALU and the registers that connected to it in atmega32 processor

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In datasheet of atmega32 written:

 

"The Atmel®AVR®AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers".

 

I have a question how the ALU is connected to the 32 registers and what is the meaning by "allowing two independent registers to be accessed "?
 

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I am living to bring up new earth ,and not to eat and destroy earth.

Last Edited: Sat. Jul 28, 2018 - 09:41 PM
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It means that specified registers are switched to the ALU input and output based on the register bits of corresponding instructions, e.g. add r3,r4.  In older designs you might need to do lda variable1, add variable2, sta variable1.  (brings back memories of my 6502 days)

Last Edited: Sat. Jul 28, 2018 - 04:55 PM
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Here, I found this diagram:

 

Image result for avr alu analysis

 

The ALU of the AVR reads any 2 registers directly, performs an operation, then stores the result in one of these 2 registers. There are other architectures with several different schemes, for example, the ALU could be connected to RAM directly, any register could be selected for the output, or a specific register ("accumulator") is always the output.

 

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The Mega32 spec sheet has a convenient diagram, part of which is shown in the attachment.

 

It shows, effectively, a separate "bus" between the ALU and the "working registers". Note that there are also other things in there called "registers" which control various operating details and peripherals. These control registers are part of the SRAM and are addressed within the SRAM address space. Working registers have an independent address space THOUGH the Mega32 memory map (as is also the case for all Mega and Tiny devices) IS addressable within the SRAM address space as shown in the second attachment.

 

Note that the diagram shows a data bus shared by SRAM and the working registers. One implication of the diagram is that ALL data used by the ALU passes through the working registers.

 

Jim

 

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Jul 28, 2018 - 07:35 PM
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Mohamed asaad wrote:

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle.

I have a question how the ALU is connected to the 32 registers and what is the meaning by "allowing two independent registers to be accessed "?

Think of three 8-bit by 32-position digital switches, all connected to all 32 working registers.  One input to the ALU runs through one of the switches, and its setting is controlled by bits in the instruction.  The other input to the ALU runs through another switch, and the output runs through the 3rd switch, and both of these switches are controlled, together (always the same settings for both switches) by other bits in the instruction.  This is how e.g. add r3,r4 moves data from r3 and r4 into the ALU, and moves the result back to r3.  The assembler converts the text "r3,r4" into the correct register select bits (correct "switch settings") for the instruction.

 

As an aside, some architectures go one step further, and allow the 2nd and 3rd switches in the example to have independent settings.  So you might see add r1,r2,r3, where r2 and r3 are added and stored back into r1.

Last Edited: Sat. Jul 28, 2018 - 07:48 PM
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For comment #4

 

You mean that  working registers are all the  registers of all peripherals or what because i think that all registers work?(i need only explanation for it )

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Last Edited: Sat. Jul 28, 2018 - 08:00 PM
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Mohamed asaad wrote:

You mean by working register that all resisters of all peripherals or what because i think that all registers work?

 

Look at the instruction set manual.

 

Which registers can be directly used in an ALU operation? If they can then they must be connected to it.

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#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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The 32 working registers are the ONLY ones that you can do "arithmetic" operations on (well, logical operations, also). Both arithmetic and logical operations are done by the ALU. These 32 working registers have direct connections to the ALU. In fact, it is so direct that the ALU can use values in one or two working registers and put a result back into a working register all in one machine cycle. The working registers are the ONLY registers for which this is true. 

 

Now, if you are asking HOW this direct register-ALU connection works, then you will have to keep asking because nobody, here, can tell you. That is because nobody, here, knows those details. And THAT is because Atmel/Microchip does not document that. In the end, if this is what you are asking, you simply have to accept that it works as it is supposed to work. And, you should not care how it works, because the only thing you would learn from that is how to make an AVR of your own, and you don't need to do that. Or, do you?

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Sat. Jul 28, 2018 - 08:32 PM
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for comment number 5 :

you explained it very well ,but could you tell me how it is connected to all the 32 registers logically (i mean is there are Combinational and sequential gates that represent what you explained as a switch easily)?

I am living to bring up new earth ,and not to eat and destroy earth.

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As mentioned in #8, the actual implementation is not described. We can only assume a 1 of n decoder is used to select the required register. We could also guess that the register bank is implemented as a dual port memory.

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Mohamed asaad wrote:

for comment number 5 :

you explained it very well ,but could you tell me how it is connected to all the 32 registers logically (i mean is there are Combinational and sequential gates that represent what you explained as a switch easily)?

All output bits of all 32 registers perhaps pass through tri-state gates, and a 1-of-N decoder enables only the gates for a given register (based on the register encoding bits in the instruction) to pass that register data to the ALU input (same for the other ALU input).  On the ALU output side, it may be that the output data is presented to all 32 registers, but a write strobe is only generated for the chosen destination register (again, involving a 1-of-N decoder).  I bet with a little searching you can find online some detailed logic info for a simple processor that covers these things in good detail.

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It might be helpful to compare the AVR diagram to "a conventional CISC architecture" from the day, like an 8051.

 

8051 architecture

 

Each ALU operation on an 8051 uses "the databus" for one operand, and MUST use the "Accumulator" for the other operand.

That tends to make the Accumulator quite a bottleneck when it comes to performing and sort of complex operand - temporary results have to be manually stored in memory, which is slower than registers.